The working engineer’s guide to FPGAs
Structured lessons from your first look-up table to research-grade architecture, deep-dive topic hubs, honest vendor and board references, and daily news written in plain English with sources linked.
Learning tracks
All lessons →Beginner
From “what is an FPGA?” to your first synthesised design on a real board.
Intermediate
Timing, constraints, clock domains, verification and bus interfaces.
Advanced
SoC FPGAs, high-speed I/O, DSP pipelines and hardware acceleration.
Expert
Architecture research, CAD algorithms, security and the open-source frontier.
Start here
Full beginner track →What is an FPGA?
A field-programmable gate array is a chip whose logic you wire up yourself. This lesson explains what that means, how it differs from a microcontroller, an ASIC and a GPU, and where FPGAs earn their keep
How an FPGA is programmed
The path from a hardware description to a configured chip, step by step, with the tool names you will meet at AMD, Altera, Lattice and in the open-source flow
Combinational logic and look-up tables
Boolean functions, truth tables and how a look-up table turns any of them into a small memory, plus carry chains and multiplexers, with a combinational block in Verilog and VHDL
Registers, clocks and the idea of state
Flip-flops, clock edges, setup and hold explained intuitively, the synchronous design rules that keep a design predictable, and a register with synchronous reset and enable in Verilog and VHDL
Your first HDL module
The anatomy of a Verilog module and a VHDL entity, ports, wires, regs and signals, continuous and clocked assignment, and a complete blinking-LED counter in both languages explained line by line
Simulation and testbenches
Why you simulate before you synthesise, how a Verilog or VHDL testbench drives a design, and how to read the waveform it produces.
Topic hubs
All 20 topics →FPGA architecture
LUTs, routing, block RAM, DSP slices and clocking.
Hardware description languages
VHDL, Verilog, SystemVerilog and the generators above them.
High-level synthesis
Turning C, C++ and SYCL into RTL, and when that pays off.
Verification
Testbenches, cocotb, UVM, formal and CI for hardware.
Timing closure and constraints
STA, XDC and SDC, clock domain crossing and resets.
SoC FPGAs
Zynq, Versal, Agilex SoC and PolarFire SoC with Linux.
Soft processors
MicroBlaze V, Nios V, VexRiscv, NEORV32 and LiteX.
High-speed I/O
Transceivers, PCIe, Ethernet, DDR, HBM and JESD204.
DSP on FPGA
Fixed point, DSP slices, filters, FFTs and CORDIC.
Wireless and SDR
RFSoC, OFDM, LDPC, 5G NR blocks and GNU Radio offload.
Image and video processing
Cameras, displays, streaming pipelines and bandwidth
AI and machine learning on FPGA
Quantised inference, dataflow and overlay accelerators
Vendors
Vendor hubs →Build something
All projects →From blinky to PWM breathing LEDs on the Tang Nano 9K with open-source tools
Install Yosys, nextpnr-himbaechel and openFPGALoader, then make the six LEDs on the Tang Nano 9K breathe with a triangle wave, a gamma lookup and a PWM module you write yourself.
UART echo on the Basys 3
Build a 115200-baud UART receiver and transmitter in Verilog, echo typed characters back with their case toggled, simulate it, then test it from a serial terminal.
VGA test pattern on the iCEBreaker
Generate 640x480 at 60 Hz from an iCE40 UP5K with the open-source flow, with a PLL-derived pixel clock, a sync generator, colour bars, a chequerboard and a bouncing block on a 12-bit VGA Pmod.