Achronix
A high-end specialist whose 7 nm Speedster7t devices combine a hard 2D network on chip, GDDR6 and 400G Ethernet for data centre and networking work, plus Speedcore eFPGA IP.
| Headquarters | Santa Clara, California, USA |
|---|---|
| Website | www.achronix.com/ |
| Toolchain | ACE (Achronix CAD Environment) with bundled Synplify Pro, Snapshot debugger, VectorPath card software stack |
| Licensing | ACE licences are paid and node-locked or floating; evaluation licences are available on request at the time of writing |
| Updated | 13 Nov 2026 |
Device families #
| Family | Process | Logic | Positioning |
|---|---|---|---|
| Speedster7t (AC7t1500, AC7t800) | 7 nm | about 300k-692k 6-input LUTs | Data centre and networking accelerator FPGA with hard 2D NoC, GDDR6, PCIe Gen5 and 400G Ethernet |
| Speedcore eFPGA IP | 16 nm, 7 nm and others on request | sized per customer | Embedded FPGA fabric for customer ASICs |
Who they are
This page is for engineers working on high-throughput acceleration, packet processing or machine learning inference who need more memory bandwidth than a conventional FPGA offers, and for ASIC designers evaluating embedded FPGA IP. Achronix was founded in 2004 and shipped its first Speedster devices on Intel’s 22 nm process in the early 2010s. It then concentrated on Speedcore eFPGA IP, which it licensed to several large customers, before returning to standalone devices with the 7 nm Speedster7t in 2019.
The company’s distinguishing feature is the two-dimensional network on chip. Rather than routing traffic from a PCIe or GDDR6 interface across the FPGA fabric, the Speedster7t carries it on a hard NoC with bandwidth in the tens of terabits per second, and the user logic attaches at access points. AMD’s Versal has a similar idea, but Achronix shipped it first and pairs it with GDDR6 rather than HBM, which lowers the cost of high memory bandwidth.
Toolchain
You install ACE, which runs on 64-bit Linux and Windows. Synthesis is Synplify Pro, bundled and licensed through ACE. Place and route, timing analysis, bitstream generation and the Snapshot in-fabric debugger are Achronix’s own. Licences are paid, and there is no free edition. Evaluation licences are available to engaged customers. The VectorPath accelerator card comes with a PCIe driver, a runtime library and reference designs that wrap the NoC, GDDR6 and Ethernet in a framework so you can attach your kernel.
The IP library covers the hard blocks, including the NoC access points, GDDR6 and DDR4 controllers, the 400G Ethernet MACs and the PCIe Gen5 controllers, plus the usual soft FIFOs, memories and arithmetic. There is no HLS tool from Achronix, though third-party HLS flows have targeted it.
Pain points: a small user base means few public examples. ACE is competent but less polished than Vivado. The paid licence and the cost of the card put the platform out of reach for individuals.
Boards to start with
- The VectorPath S7t-VG6 is the only mainstream Achronix board: a PCIe Gen4 x16 card carrying an AC7t1500, 16 GB of GDDR6, 4 GB of DDR4 and two QSFP-DD cages.
There is no low-cost evaluation board. If you want to learn the architecture, the best route is the documentation, the ACE evaluation licence and the public reference designs, or access through a cloud or university programme if one is available.
Migration notes
Coming from AMD or Altera, the fabric looks familiar: 6-input LUTs, block RAM, and DSP-like machine learning processor (MLP) blocks that handle integer matrix arithmetic with built-in accumulators and a small attached memory. Synplify Pro synthesises your RTL, so syn_ attributes apply, and timing constraints are standard SDC. Physical constraints are in Achronix’s own .pdc format with pin and placement commands.
The change is at the system level. Interfaces to GDDR6, DDR4, PCIe and Ethernet are reached through NoC access points, which present AXI interfaces inside the fabric wherever you place them. You do not route a 512-bit bus from an edge controller across the die. Design the NoC traffic map first, then the kernels. The MLP blocks reward designs written for them: a conventional multiply-add chain will map but will not reach the headline throughput.
Clocking is through PLLs and a global clock network with regional trunks, as on other 7 nm devices, and the NoC runs on its own clock. There is no block design canvas, so top-level stitching is RTL.
Watch for
This is a platform for funded engineering teams, not a hobby device. Two devices exist in the family and the smaller AC7t800 has limited board support. The NoC is a real benefit but also a dependency: a design that does not fit the NoC model gives up most of the advantage. GDDR6 is graphics memory, with high bandwidth but higher latency and tighter PCB design rules than DDR4. Public benchmarks are vendor-produced, so test your own kernels before committing. Support is responsive but the public forum is small, and most knowledge is inside the company and its lead customers.