Renesas (ForgeFPGA)
Tiny ForgeFPGA devices of one to five thousand LUTs, descended from the Silego and Dialog mixed-signal line, sold as a programmable replacement for glue logic at a sub-dollar price point.
| Headquarters | Tokyo, Japan |
|---|---|
| Website | www.renesas.com/en/products/programmable-mixed-signal-asic-ip-products/forgefpga-low-density-fpgas |
| Toolchain | Go Configure Software Hub with the ForgeFPGA Workshop (Verilog entry, synthesis, place and route, emulation and programming) |
| Licensing | Free, no licence required at the time of writing |
| Updated | 13 Nov 2026 |
Device families #
| Family | Process | Logic | Positioning |
|---|---|---|---|
| ForgeFPGA (SLG47910, SLG47911 and successors) | undisclosed | about 1.1k-5k LUTs | Very small FPGAs to replace discrete logic, with an on-chip oscillator and OTP configuration memory |
Who they are
This page is for hardware designers who want programmable logic in the same role as a handful of discrete logic chips, and for anyone curious about the smallest FPGAs on the market. Renesas is a large Japanese semiconductor company best known for microcontrollers and automotive devices. It acquired Dialog Semiconductor in 2021, and Dialog had bought Silego in 2017. Silego’s product was the GreenPAK, a family of tiny configurable mixed-signal devices programmed through a drag-and-drop tool and sold for well under a dollar. ForgeFPGA, introduced in 2022, takes the same packaging, pricing and one-time-programmable approach and replaces the fixed-function GreenPAK blocks with a small LUT-based fabric.
The positioning is clear. ForgeFPGA is not meant to compete with a Lattice iCE40 on capacity. It competes with a 74-series logic chip, a small CPLD or a microcontroller running a bit-banged state machine, in a board that needs a few hundred gates of custom logic, a clock divider or a level-shifting interface.
Toolchain
You install the Go Configure Software Hub, which runs on Windows, with macOS and Linux versions at the time of writing that lag the Windows release. Inside it, the ForgeFPGA Workshop is the environment: a Verilog editor, synthesis, place and route, a pin and oscillator configurator, a waveform-based emulator and a programmer. It is free and there is no registration or licence file. The install is small.
The Workshop accepts Verilog only. Synthesis is based on Yosys with Renesas’s own mapping and place and route, which means the supported language subset is Yosys’s. There is no VHDL path and no external synthesis option. Designs are tested in an emulation mode that loads configuration into the volatile part of the device, so you can iterate without burning the OTP, and the development board carries a socket for the final programming step.
Pain points: there is no timing analyser of the kind you are used to, so timing is a matter of the datasheet’s propagation numbers and the on-chip oscillator’s tolerance. Debug is by pins. Documentation is short and the user community is small.
Boards to start with
- The ForgeFPGA evaluation board carries a socketed device, a USB programmer and breakout headers, and is the one board you need.
Renesas also sells a socket adapter for programming production parts, and sample devices are easy to obtain.
Migration notes
Coming from any mainstream FPGA, scale down your expectations. The SLG47910 has about 1,120 LUTs, a few kilobits of block RAM and no DSP. There are no PLLs: a configurable on-chip oscillator supplies the clock, with an accuracy of a few per cent, and an external clock can be brought in through a pin. There are no global clock buffers to worry about because the fabric is small enough that every net is short.
Pin assignment, oscillator settings and I/O modes are done in the Workshop’s GUI, not in a constraints file. Your Verilog top module ports map to the pins you have enabled. There is no SDC. Block RAM is instantiated through a wizard-generated primitive and inference is limited. Reset is a pin or a power-on reset block configured in the GUI.
Configuration is one-time programmable, so the workflow is: emulate, test, emulate again, and only then burn. A burned part cannot be changed, though the emulation mode works on programmed and unprogrammed parts alike. This matches how GreenPAK users have worked for years but is unlike any SRAM or flash FPGA.
Watch for
OTP means a mistake in a programmed production batch is a scrapped batch. Capacity is tiny and a design that grows slightly can fall off the edge. The toolchain is Windows-first and the Verilog subset is what Yosys supports, with no SystemVerilog features beyond what Yosys handles. Renesas is a large company and ForgeFPGA is a small product line within it, so long-term roadmap visibility is limited. Per-unit pricing is attractive but the vendor’s sub-dollar figures are for volume, and single-unit prices from distributors are higher. If you need more than a few thousand LUTs, an iCE40 or a MachXO2 is the next step up and both are also cheap.