Altera
The second-largest FPGA vendor, independent again after its years inside Intel, with Quartus Prime, the Nios V soft core and families from MAX 10 up to Agilex 9.
| Headquarters | San Jose, California, USA |
|---|---|
| Website | www.altera.com/ |
| Toolchain | Quartus Prime Lite, Standard and Pro (RTL to bitstream), Nios V (RISC-V soft core), oneAPI and HLS flows for C++ |
| Licensing | Quartus Prime Lite is free; Standard is paid; Pro is paid for most devices with free licences for some Agilex 3 and Agilex 5 parts at the time of writing |
| Updated | 13 Nov 2026 |
Device families #
| Family | Process | Logic | Positioning |
|---|---|---|---|
| MAX 10 | 55 nm | 2k-50k logic elements | Single-chip, instant-on, flash-based |
| Cyclone 10 LP | 60 nm | 6k-120k logic elements | Lowest-cost volume FPGA |
| Cyclone 10 GX | 20 nm | 85k-220k logic elements | Low-cost with 12.5 Gb/s transceivers |
| Cyclone V (incl. SoC) | 28 nm | 25k-301k logic elements | Low-cost, SoC variants with dual Cortex-A9 |
| Arria 10 | 20 nm | 160k-1,150k logic elements | Mid-range, hard floating-point DSP, SoC variants |
| Stratix 10 | Intel 14 nm | up to 10.2M logic elements | High-end, HyperFlex registers in routing, HBM and SoC variants |
| Agilex 3 | Intel 7 | 25k-135k logic elements | Low-cost and small form factor with a hard Cortex-A55 subsystem on some parts |
| Agilex 5 | Intel 7 | 50k-656k logic elements | Mid-range with asymmetric Cortex-A76 and A55 cores on SoC parts |
| Agilex 7 | Intel 10 nm SuperFin | 573k-3.85M logic elements | High-end with chiplet-based transceivers and HBM2e on M-series |
| Agilex 9 | Intel 10 nm SuperFin | see datasheet | Direct RF with integrated multi-GS/s data converters |
Who they are
This page is for engineers choosing an Altera device or moving a design to one, and for students meeting Quartus Prime for the first time. Altera was founded in 1983 and shipped some of the first reprogrammable logic devices. Intel bought the company in 2015 and sold its FPGAs under the Intel name for several years, which is why older documents say “Intel FPGA” and why Agilex parts are built on Intel process nodes. In 2024 Intel began running Altera as a standalone subsidiary under the original name, and in 2025 it sold a majority stake to the investment firm Silver Lake while keeping a minority holding. At the time of writing Altera is an independent company with its own website, licensing and support channels, and documents are being moved from Intel domains.
Altera is the clear number two in the market. Its strengths are the low-cost Cyclone and MAX 10 lines, which dominate undergraduate courses in many countries, and the high-end Stratix 10 and Agilex 7 parts used in wireless infrastructure and data centre acceleration.
Toolchain
You install Quartus Prime. There are three editions. Lite is free and covers MAX 10, Cyclone 10 LP, Cyclone IV and Cyclone V, including the SoC parts. Standard is paid and adds Arria 10 and some older families. Pro is the modern tool for Cyclone 10 GX, Arria 10, Stratix 10 and all Agilex devices. Pro is a different codebase from Standard: it has a stricter SystemVerilog parser, uses a different project file structure and requires all hard IP to be generated through Platform Designer. At the time of writing Altera offers free Pro licences for some Agilex 3 and Agilex 5 devices, so check the licensing page before assuming a cost.
Hosts are 64-bit Windows and Linux (Ubuntu, RHEL and derivatives). Download sizes run from about 2 GB for a minimal Lite install to over 30 GB for Pro with several device families. The bundled simulator is Questa for Altera, which needs a free licence that you request separately.
Nios V is the current RISC-V soft core and replaces the older Nios II. The C++ flows are in transition: the older Intel HLS Compiler is deprecated, and the oneAPI SYCL flow for FPGAs was Intel-branded, so expect name and packaging changes.
Pain points include the split between Standard and Pro, the licence server configuration for paid editions, and Platform Designer’s generated file trees, which are large and best kept out of version control.
Boards to start with
- The DE10-Lite (MAX 10) is the standard teaching board, with switches, seven-segment displays, an accelerometer and VGA.
- The DE10-Nano is a Cyclone V SoC with a dual Cortex-A9 running Linux and a large community thanks to the MiSTer retro-computing project.
- The DE1-SoC is the fuller university version of the same device with more I/O and memory.
- The Agilex 5 development kit is the entry into the current generation, though it costs far more than the Terasic boards.
Migration notes
Coming from AMD, constraints are the first change. Quartus uses a .qsf settings file for pin assignments and I/O standards, and a separate .sdc file for timing. The SDC is standard Synopsys syntax without AMD’s Tcl extensions, so create_clock, derive_pll_clocks and set_false_path do most of the work. The Timing Analyzer replaces Vivado’s timing reports.
The logic cell is the ALM (adaptive logic module), an 8-input fracturable LUT with two registers. Block RAM is M9K on older parts and M20K on Arria 10 and later. Clocking is an IOPLL or fPLL, generated as IP. Signal Tap replaces the ILA. Platform Designer replaces IP Integrator and uses Avalon interfaces by default, although AXI is fully supported and bridges are provided. Infer memory and DSP from RTL for portability. The DSP blocks on Arria 10 and later support hard IEEE 754 single-precision floating point, which AMD parts do not.
Watch for
The Intel to Altera transition means URLs, licence servers, installer names and support portals have changed and may change again. Old forum posts refer to “Intel FPGA” tools that are now renamed. The Lite edition does not support Agilex, so the cheapest route to the current generation requires Pro. Cyclone V SoC boards are good value but the device is over a decade old, and the hard processor runs an old ARMv7 core with limited upstream Linux attention. Questa licensing trips up new users, since the simulator is installed by default but refuses to run until the licence file is in place.