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Microchip

Flash-based FPGAs from the former Actel and Microsemi lines, positioned on low power, security and radiation tolerance, with the RISC-V PolarFire SoC and the Libero SoC tools.

Headquarters	Chandler, Arizona, USA
Website	www.microchip.com/en-us/products/fpgas-and-plds
Toolchain	Libero SoC (RTL to bitstream, bundles Synplify Pro and a limited ModelSim), SoftConsole (embedded software), SmartHLS (C++ synthesis)
Licensing	Free Silver licence for small and mid-range devices, renewed yearly; larger parts need a paid Gold licence at the time of writing
Updated	13 Nov 2026

Device families #

Family	Process	Logic	Positioning
IGLOO2 Instant-on, single chip, no external boot memory	65 nm	6k-150k logic elements	Low-power flash FPGA without a processor
SmartFusion2 Used widely in aerospace and industrial control	65 nm	6k-150k logic elements	Same fabric with a hard Cortex-M3
PolarFire SONOS flash configuration	28 nm	100k-481k logic elements	Mid-range, low power, 12.7 Gb/s transceivers
PolarFire SoC Runs Linux, first mainstream RISC-V SoC FPGA	28 nm	25k-460k logic elements	Quad 64-bit RISC-V (U54) plus monitor core with PolarFire fabric
RTG4 Hardened flip-flops, no configuration upsets	65 nm	150k logic elements	Radiation-tolerant flash FPGA for space
RT PolarFire Qualified to QML Class V at the time of writing	28 nm	481k logic elements	Radiation-tolerant PolarFire
RT PolarFire SoC Early availability at the time of writing, check status	28 nm	460k logic elements	Radiation-tolerant RISC-V SoC FPGA

Who they are

This page is for engineers who need a flash-based FPGA, which usually means low power, no external configuration memory or tolerance to radiation. Microchip’s FPGA business descends from Actel, founded in 1985, which built antifuse and later flash devices for military and space customers. Microsemi bought Actel in 2010, and Microchip bought Microsemi in 2018. The business is smaller than AMD or Altera but holds a strong position in satellites, aircraft, defence and industrial equipment, where a part that is live at power-up and cannot be read back has real value.

The two things to know are that the configuration lives in on-chip flash, so there is no bitstream to load at boot and no SRAM configuration to upset, and that PolarFire SoC was the first mainstream SoC FPGA with hard RISC-V cores.

Toolchain

You install Libero SoC, which runs on 64-bit Windows and on RHEL-compatible Linux and Ubuntu. The installer is a few gigabytes. Synthesis is Synplify Pro from Synopsys, bundled and licensed through Libero, and simulation is a limited ModelSim or Questa build. SmartDesign is the block-level canvas, and the Firmware Catalog pulls drivers for the hard IP. SoftConsole is the free Eclipse-based IDE for Cortex-M3 and RISC-V software. SmartHLS compiles C++ to RTL and comes from the LegUp acquisition.

Licensing at the time of writing has a free Silver tier that covers the IGLOO2 and SmartFusion2 range, the smaller PolarFire parts and the PolarFire SoC parts on the common boards. The licence is node-locked and renewed yearly through the website. Larger PolarFire devices and the RT parts need a paid Gold licence. Check the licence comparison before choosing a device, because the boundary has moved more than once.

Pain points are a GUI that feels older than Vivado or Quartus, a Linux install that needs a list of 32-bit compatibility packages, and a heavier dependence on vendor-generated wrappers for memory, clocking and I/O. Compile times are modest because the devices are modest.

Boards to start with

The PolarFire SoC Icicle Kit is the reference board for the RISC-V SoC, with Linux, PCIe, Ethernet and Raspberry Pi and mikroBUS headers.
The BeagleV-Fire puts the same device on a BeagleBone-sized board at a lower price, with an open hardware design.
The SmartFusion2 Maker Kit is the cheap way to try the Cortex-M3 family and the Libero flow.

There are also PolarFire evaluation and video kits for transceiver work, but they cost far more.

Migration notes

Coming from AMD or Altera, synthesis is Synplify Pro, so attributes are syn_keep, syn_preserve and syn_ramstyle rather than KEEP or ramstyle. Timing constraints are standard SDC in a .sdc file, and physical constraints go in a .pdc file with set_io commands for pins and I/O standards. The clock conditioning circuit (CCC) replaces MMCM, PLL and IOPLL, and it is almost always generated through the configurator rather than instantiated by hand. Fabric memories are LSRAM (large, 20 kbit on PolarFire) and uSRAM (small, 64 by 12), and the math block is MACC_PA. Inference works for simple cases but the configurator gives you more control over ECC and port modes.

There is no configuration memory to program and no equivalent of a bitstream readback. Programming uses FlashPro hardware or the on-board programmer, and the device starts running at power-up. On the SoC, the hard cores boot from on-chip eNVM through the Hart Software Services, which replace the first-stage boot loader you may know from Zynq. The RISC-V cores run mainline Linux, and the Yocto and Buildroot flows are maintained on GitHub.

Watch for

Device choice is narrower than at AMD or Altera, and there is no equivalent to the largest UltraScale+ or Agilex 7 parts. Transceiver speeds top out at 12.7 Gb/s. Flash parts have a limited number of programming cycles, which is not a problem in use but matters if you reprogram hundreds of times in a day during bring-up. Synplify Pro licensing within Libero can expire separately from the Libero licence. The RT parts are expensive and lead times are long, and the commercial and RT versions have different package and speed grades, so a design validated on a commercial device still needs checking. Documentation is thorough but spread across many short application notes rather than a few long user guides.