SoC FPGAs

Overview

An SoC FPGA puts one or more hard processor cores, their memory controller and standard peripherals on the same die as programmable logic. The processor side runs Linux or an RTOS and handles networking, storage and control. The logic side does the parts that software cannot do fast enough. This hub is for engineers who need to understand how the two halves talk, how the chip boots, and which parts of the vendor flow are worth learning first.

The idea has been mainstream since AMD (then Xilinx) shipped Zynq 7000 in 2011 with two Arm Cortex-A9 cores. Today the field includes Zynq UltraScale+ MPSoC (quad Cortex-A53 plus dual Cortex-R5), Versal (dual Cortex-A72 and Cortex-R5F, plus AI Engines on some parts), Altera’s Agilex SoC families with Cortex-A53 or Cortex-A76 cores, and Microchip’s PolarFire SoC, which was the first to use RISC-V (SiFive U54 cores) in a production FPGA.

Key ideas

The PS/PL boundary

AMD’s names have stuck: the processing system (PS) is the hard part and the programmable logic (PL) is the fabric. Altera calls them HPS and FPGA fabric. Microchip calls the processor cluster the MSS. The boundary is a set of AXI ports. General-purpose master ports let the processor write registers in your logic. High-performance slave ports let your logic write directly into DDR at full bandwidth. A coherent port (ACP on Zynq 7000, ACE or the CCI on MPSoC) lets logic read the processor’s caches without software flushing them. Interrupts cross in the other direction. Everything else, clocks and resets included, is routed through this interface, and the system you build is mostly a decision about which ports carry what.

Boot flow

Power-on starts a boot ROM inside the processor. It reads a first-stage boot loader (FSBL on Zynq 7000, FSBL plus PMU firmware on MPSoC, PLM on Versal, HSS on PolarFire SoC) from QSPI flash, SD card or eMMC. That loader initialises DDR, optionally programs the PL with a bitstream, and hands over to U-Boot, which loads a Linux kernel and device tree. On Versal the boot image is a PDI that programs the device in stages. On MPSoC, Arm Trusted Firmware sits between the FSBL and U-Boot. Debugging a board that does not boot means knowing which stage printed last, so the serial console is the first thing to connect.

Device tree, drivers and the vendor Linux flows

Linux learns about your logic through the device tree: a text description of which IP sits at which address with which interrupt. AMD’s tools generate a device tree overlay from the hardware design, and Altera’s tools do the same from the Platform Designer system. A register block with an AXI-Lite interface can then be reached from user space through UIO or a small platform driver. PetaLinux is AMD’s wrapper around Yocto that hides most of the Yocto layer structure. Altera and Microchip document Yocto directly, and many teams use Buildroot for small images. Whichever you choose, the vendor’s board support package is a starting point, not a finished product, and keeping your patches in a separate layer saves pain at the next tool release.

Which family

Zynq 7000 remains the cheapest way to get Linux beside logic and is widely supported by low-cost boards. MPSoC adds 64-bit cores, a GPU, real-time cores and much more fabric, and is the mainstream choice for vision and industrial work. Versal is the newest and brings a network on chip and AI Engines, at the cost of a new boot model and a steeper learning curve. Agilex SoC parts are strong on transceiver bandwidth and memory interfaces. PolarFire SoC is the low-power and radiation-tolerant choice, and the only one with RISC-V at the time of writing.

Where to start

• /learn/beginner/01-what-is-an-fpga/ explains why a processor and logic complement each other.
• /learn/beginner/09-memories-block-ram-and-fifos/ covers the FIFOs that every PS/PL data path uses.
• /learn/beginner/10-from-rtl-to-board/ builds a pure-logic design that you will later wrap in an AXI interface.

Intermediate lessons on a first AXI-Lite peripheral, a PetaLinux build and DMA from logic into Linux memory are coming.

Tools and vendors

Core counts above are the common configurations at the time of writing. Check the specific part.

Common mistakes

• Sending bulk data through a general-purpose port one word at a time instead of using DMA through a high-performance port.
• Forgetting cache coherency, so Linux reads stale data from a buffer the logic has filled.
• Hand-editing the generated device tree instead of adding an overlay, then losing the edits on the next export.
• Asserting the logic’s reset from a processor register while the logic is still driving an AXI transaction, which hangs the interconnect.
• Treating the vendor board support package as production firmware.
• Starting on Versal for a first SoC project when a Zynq 7000 board would teach the same lessons for a tenth of the price.

Going deeper

• AMD UG585, Zynq 7000 SoC Technical Reference Manual: the register-level description of the original SoC FPGA.
• AMD UG1085, Zynq UltraScale+ Device Technical Reference Manual: the MPSoC equivalent.
• AMD UG1144, PetaLinux Tools Reference Guide: the build flow and how it wraps Yocto.
• AMD UG1037, Vivado AXI Reference Guide: AXI4, AXI4-Lite and AXI4-Stream as used in the vendor IP.
• Arm AMBA AXI specification: the protocol itself.
• Microchip PolarFire SoC documentation: landing page for the RISC-V SoC FPGA.
• Yocto Project documentation: the layer system under PetaLinux and the Altera and Microchip flows.