NanoXplore
A French vendor of radiation-hardened SRAM FPGAs, from NG-Medium to the 28 nm FD-SOI NG-Ultra with Cortex-R52 cores, built with ESA and CNES for European space independence.
| Headquarters | Sèvres, France |
|---|---|
| Website | www.nanoxplore.com/ |
| Toolchain | NXmap (synthesis, place and route, bitstream), NXscope debugger, NXcore IP, ARM and third-party software tools for NG-Ultra processors |
| Licensing | NXmap is paid and node-locked or floating; evaluation licences are issued to customers and institutions at the time of writing |
| Updated | 13 Nov 2026 |
Device families #
| Family | Process | Logic | Positioning |
|---|---|---|---|
| NG-Medium | 65 nm | about 34k LUTs | Radiation-hardened by design, mid-sized space FPGA |
| NG-Large | 65 nm | about 137k LUTs | Larger rad-hard FPGA with a hard Cortex-R5 and 6.25 Gb/s SERDES |
| NG-Ultra | 28 nm FD-SOI | about 536k LUTs | Highest capacity European rad-hard SoC FPGA with quad Cortex-R52 and 12.5 Gb/s SERDES |
Who they are
This page is for engineers in space, defence and high-reliability programmes, especially in Europe, where supply of radiation-hardened FPGAs has historically depended on export licences from the United States. NanoXplore was founded in 2010 near Paris and developed its first rad-hard devices with support from the French space agency CNES, the European Space Agency and the European Commission’s non-dependence programmes. NG-Medium flew first, NG-Large followed with an embedded Cortex-R5, and NG-Ultra, the result of the DAHLIA project with Airbus, Thales Alenia Space and STMicroelectronics, brings a quad-core Cortex-R52 subsystem and a 28 nm FD-SOI fabric.
The devices are SRAM-based but hardened by design: configuration memory and user flip-flops use radiation-tolerant cell structures, and the parts are specified for total ionising dose and single-event effects without external scrubbing. That is a different approach from Microchip’s flash parts and from the triple-redundant SRAM designs some AMD space customers use. See the space and high-reliability topic.
Toolchain
You install NXmap, which runs on 64-bit Linux, with Windows support that has lagged behind. It includes its own synthesis, place and route, timing analysis and bitstream generation, driven mainly from Python scripts with a GUI for viewing results. Synplify Pro can be used as an alternative front end. NXscope is the in-fabric logic analyser. For the processor subsystems on NG-Large and NG-Ultra, you use the standard ARM toolchain and a board support package from NanoXplore, with RTEMS and Linux ports available from partners.
Licensing is paid and tied to a programme or an institution, and the vendor is used to dealing with agencies and primes rather than individuals. Evaluation licences exist. At the time of writing there is no free edition.
Pain points are those of a small vendor in a specialised market: a short list of supported IP, a Python-driven flow that is unlike the Tcl flows elsewhere, documentation that assumes a space-industry reader, and a user community that is small and mostly under non-disclosure.
Boards to start with
- The NG-Ultra development kit is the vendor’s evaluation board for the NG-Ultra, with the processor subsystem, memory, SERDES and debug connectors broken out.
Development kits exist for NG-Medium and NG-Large too, and commercial-grade versions of the devices are offered for ground equipment and prototyping before you commit to flight parts. There is no hobby-priced board.
Migration notes
Coming from AMD, where most European space teams start, the fabric is 4-input LUTs with carry chains, block RAMs of 48 kbit, DSP blocks with 24-bit by 24-bit multipliers, and a set of PLLs and global clock buffers. Capacity in LUTs is therefore not directly comparable to a 6-input-LUT device. Memory and DSP inference work, but NanoXplore encourages instantiation through its primitives for flight designs so that configuration and protection options are explicit.
Constraints are set through the NXmap Python API rather than XDC or SDC files, though SDC import is supported for timing. Pin placement, I/O standards and timing constraints become method calls on the project object, which makes scripted flows natural but is a surprise if you expect a constraints file. Clocking uses the device’s PLLs with dedicated input pins and there is no equivalent of the clocking wizard.
Mitigation features are built into the device, so you do not add triple modular redundancy to the fabric by default. Review the radiation reports for your part and orbit before deciding what, if anything, to add at the design level.
Watch for
The company is small and its roadmap depends on agency funding and a few large programmes, so schedules have slipped in the past. NG-Ultra qualification was still in progress at the time of writing, so check the current ESCC and ECSS status for the exact part you intend to fly. Tool maturity trails the commercial vendors, and some engineers report needing vendor support for timing closure on dense designs. Export rules apply to these parts too, under French and European controls, and the commercial versions do not escape that. Pricing is in the range expected for space-grade parts, which is many thousands of euros per device.