Glossary
220 terms, each defined in one or two sentences, with links to where the idea is explained properly.
0–9
- 8b/10b and 64b/66b encoding
- Line codes that keep a serial stream DC balanced with enough transitions for clock recovery. 8b/10b maps each byte to 10 bits at 25 percent overhead (PCIe Gen1 and 2, gigabit Ethernet), while 64b/66b adds two sync bits per 64-bit block at 3 percent (10 gigabit Ethernet and later).
A
- Accelerator card
- A PCIe card carrying a large FPGA, often with DDR or HBM and network ports, installed in a server to run work offloaded from the CPU. AMD Alveo and Altera Agilex cards are typical.
- ALM (adaptive logic module)
- Altera's logic tile, with an 8-input fracturable LUT, two full adders and up to four registers. It can implement two smaller independent functions or one wide one, and resource reports count half-ALMs as ALUTs.
- Always block
- A Verilog procedural block that re-executes whenever a signal in its sensitivity list changes. The SystemVerilog forms always_ff and always_comb state the intent and let tools check it.
- Amaranth
- A Python-embedded hardware description language, formerly nMigen, with a clean synchronous design model and a built-in simulator. It generates Verilog for any toolchain.
- Anti-tamper
- Measures that detect or respond to physical attack, including voltage and temperature monitors, mesh sensors and key zeroisation. Battery-backed keys exist so they can be erased, and defence programmes require it.
- Arbitrary precision types
- C++ types such as ap_int<13> or ac_fixed<16,4> that let HLS code use exactly the bit widths the hardware needs instead of a 32-bit int. They are essential for area and timing.
- Architecture (VHDL)
- In VHDL, the body that implements an entity, containing signals, processes and component instances. Named architectures let you keep a behavioural and a structural version of the same entity side by side.
- ASIC (application-specific integrated circuit)
- A chip designed and fabricated for one purpose. Faster and cheaper per unit than an FPGA at volume, but with high NRE, long lead times and no way to fix a bug after tape-out.
- Assertion
- A statement of a property that must hold, checked during simulation or proved by formal tools. SystemVerilog Assertions and PSL can express sequences such as a request being followed by a grant within four cycles.
- Asynchronous FIFO
- A first-in first-out buffer with separate write and read clocks, comparing Gray-coded pointers through synchronisers to produce full and empty flags. The safe way to move multi-bit data between clock domains.
- Asynchronous reset
- A reset that acts on flip-flops regardless of the clock, using their dedicated reset pin. It works without a running clock, but its release must be synchronised or registers can come out of reset in different cycles.
- Authentication
- Checking that a bitstream or boot image came from its legitimate author, using an RSA or ECDSA signature or an HMAC verified before loading. Encryption hides the design, authentication stops substitution.
- Avalon
- Altera's on-chip bus family, with memory-mapped and streaming variants that mirror AXI4 and AXI4-Stream. Platform Designer bridges between the two automatically.
- AXI interconnect
- The crossbar or shared bus that joins AXI masters to slaves, decoding addresses and converting data widths and clocks on the way. AMD and Altera both generate one from a graphical block design, along with the memory map.
- AXI4
- The Arm AMBA memory-mapped bus with separate read and write address, data and response channels, supporting bursts of up to 256 beats. It is the backbone of AMD IP and most modern SoC designs.
- AXI4-Lite
- A cut-down AXI4 with no bursts and one outstanding transaction, meant for control and status registers. It is small to implement and is the usual slave interface on custom IP, with APB as the even simpler Arm alternative.
- AXI4-Stream
- A point-to-point streaming protocol with data, valid and ready handshake plus optional last, keep and user signals. Used for video, DSP and network pipelines where there is no address.
B
- BGA (ball grid array)
- The package type of nearly every FPGA beyond the smallest, with solder balls on a grid under the die at a pitch of 1.0 mm, 0.8 mm or 0.5 mm. Finer pitch needs costlier boards with smaller vias to escape the inner balls.
- Bit growth
- The widening of a result beyond its inputs. Adding two N-bit numbers needs N+1 bits and multiplying them needs 2N, so a filter accumulator must be sized for the worst case or it overflows.
- Bitstream
- The binary file produced at the end of the flow that configures a device, loaded over JTAG or from flash at power-up. A mid-range device needs tens of megabits, and the format is vendor specific and mostly undocumented.
- Bitstream encryption
- Encrypting the configuration file, usually with AES-256, so only a device holding the matching key in eFuse or battery-backed RAM can load it. It protects a design from copying and reverse engineering.Hub: hardware security. Related: Authentication, eFuse, Bitstream, DPA (differential power analysis)
- Blocking assignment
- Verilog's = assignment, which updates the variable at once within the procedural block. Use it in combinational always blocks and for temporaries, never for registers.
- Bootloader
- The first software to run after reset, which initialises clocks and memory and loads the next stage. SoC FPGAs chain a vendor first-stage loader (FSBL), then U-Boot, then Linux, and the bitstream can be loaded at any of those stages.
- Bounded model checking
- A formal technique that unrolls the design for N cycles from reset and searches for any input sequence that violates an assertion. It finds bugs but cannot prove their absence beyond N, which is where k-induction takes over.
- BRAM (block RAM)
- Dedicated memory tiles spread through the fabric, each with two independent ports and configurable width. AMD blocks hold 36 kb and Altera M20K blocks 20 kb, and AMD's larger 288 kb UltraRAM serves deep buffers.
- BUFG (global clock buffer)
- AMD's primitive that launches a signal onto the dedicated global clock network, which reaches every flip-flop with skew in the tens of picoseconds. Devices have a limited number, often 32, so only real clocks and large resets belong on them.
C
- C simulation and co-simulation
- C simulation runs HLS source as ordinary software against a test harness to check the algorithm in seconds. Co-simulation then drives the generated RTL with the same harness to confirm the hardware matches and to measure real latency.
- Cache coherency
- Keeping the processor caches and fabric masters consistent when both touch the same memory. Coherent ports (ACP, ACE, CHI) handle it in hardware, while non-coherent ports need the software to flush and invalidate caches.
- Carry chain
- Dedicated adder logic and fast vertical wiring between neighbouring LUTs that passes carries without entering general routing. Adders, counters and comparators built on it run several times faster than LUT-only versions.
- CDC (clock domain crossing)
- Any path between registers on asynchronous clocks. Each crossing needs a synchroniser, handshake or dual-clock FIFO, plus a clock group constraint so STA does not report it.
- Chiplet
- A small die designed to be combined with others in one package, so fabric, transceivers and memory can be made on different processes. Large FPGAs and adaptive SoCs are chiplet assemblies.
- Chisel
- A Scala-embedded hardware construction language from Berkeley that generates Verilog through the FIRRTL intermediate representation, now compiled by the LLVM CIRCT project. Rocket, BOOM and many RISC-V cores are written in it.
- CIC filter
- A cascaded integrator-comb filter, a multiplier-free decimator or interpolator built from integrators and differentiators. It is the standard first stage after a high-rate ADC.
- CLB (configurable logic block)
- AMD's name for the tile that groups LUTs, flip-flops, multiplexers and carry logic. In UltraScale devices one CLB holds eight 6-input LUTs and sixteen flip-flops, while older 7 series parts split each CLB into two slices.
- Clock enable
- A control input on a flip-flop that holds the current value while low, without touching the clock itself. Use it instead of a derived or gated clock whenever part of a design runs slower than the rest.
- Clock gating
- Stopping the clock to idle logic to save dynamic power. In an FPGA use clock enables or the dedicated gated clock buffers such as BUFGCE, never a LUT in the clock path.
- Clock group
- A constraint declaring that two clocks are asynchronous, so STA stops analysing paths between them. Those crossings must then be handled by synchronisers or dual-clock FIFOs.
- Clock skew
- The difference in arrival time of the same clock edge at two flip-flops. Positive skew helps setup and hurts hold, which is why global clock networks are built to keep it tiny.
- Clock-to-Q delay
- The time from a clock edge to a flip-flop's output changing, typically a few hundred picoseconds in current devices. It is the first term in every register-to-register path.
- cocotb
- A Python framework that drives a Verilog or VHDL simulation through coroutines, so the testbench is Python with pytest-style structure. It works with Icarus, Verilator, GHDL and the commercial simulators.
- Configuration memory
- The SRAM cells that hold the bitstream and set every LUT, routing switch and option in the device. It is empty at power-up and vulnerable to single-event upsets, which flash-based and antifuse FPGAs avoid.
- Constrained random
- Generating stimulus at random within declared constraints, so many legal cases are reached without writing each one by hand. Coverage then shows what the randomness actually hit.
- Constraints
- Statements that tell the tools what the design needs, including clock periods, I/O timing, pin assignments and exceptions. Paths without constraints are not checked, so a missing constraint is a silent failure.
- CORDIC
- An iterative shift-and-add algorithm that computes sine, cosine, magnitude and phase without multipliers. It gains about one bit of precision per iteration and pipelines well.
- Coverage
- Measures of how much of a design a test suite exercised. Code coverage counts lines and branches executed, while functional coverage counts user-defined events such as the FIFO becoming full.
D
- Dataflow (HLS)
- An HLS pragma that lets sequential functions run concurrently with FIFOs or ping-pong buffers between them, so a producer and a consumer overlap. It is the task-level counterpart of loop pipelining.
- Dataflow architecture
- An accelerator in which each layer of a network gets its own hardware and data streams straight between them, with no instruction fetch or shared memory. FINN and hls4ml generate this style.
- DDR SDRAM
- Dynamic memory that transfers data on both clock edges, in generations from DDR3 to DDR5 and the low-power LPDDR4 and LPDDR5 variants. Its controller and PHY are the hardest common interface to bring up, so hard controllers in the silicon are worth paying for.
- Decimation and interpolation
- Decimation lowers the sample rate by keeping every Nth sample after a low-pass filter prevents aliasing. Interpolation raises it by inserting zeros and filtering out the images. CIC and polyphase FIR filters do both efficiently.
- Device tree
- A data structure that tells the Linux kernel what hardware exists, with each peripheral's address and interrupts. On an FPGA it must be regenerated whenever the fabric design changes.
- DFX (Dynamic Function eXchange)
- AMD's current name for partial reconfiguration in Vivado.Hub: fpga architecture.
- Distributed RAM (LUTRAM)
- Small memories built from the LUTs themselves in slices that allow it, usually 64 bits per LUT. Suited to shallow register files and small FIFOs where a whole BRAM would be wasted.
- DMA (direct memory access)
- A hardware engine that moves data between memory and peripherals without the CPU copying each word. In SoC FPGAs it bridges AXI4-Stream pipelines to DDR, and the video variant (VDMA) manages whole frames.
- DPA (differential power analysis)
- Statistically correlating many power traces with guessed key bits to recover a cipher key. It is the reason bitstream decryptors now use masking and key rolling.
- DPU (deep learning processing unit)
- AMD's configurable overlay for convolutional networks on Zynq and Versal devices, programmed through the Vitis AI compiler. Other vendors ship equivalents under different names.
- DSP slice
- A hard arithmetic block with a multiplier, adder, accumulator, pre-adder and pipeline registers. An AMD DSP48E2 multiplies 27 by 18 bits, and an Altera variable-precision block handles two 18 by 19 multiplies or one single-precision float.
- DUT (device under test)
- The design instance that a testbench exercises, also called the unit under test (UUT). Keeping it as a plain instance with no test code inside means the same RTL goes to synthesis.Hub: verification. Related: Testbench
- Dynamic power
- Power consumed by switching, proportional to capacitance, the square of the supply voltage, clock frequency and the fraction of nodes that toggle each cycle. Clock trees and high-toggle data paths dominate it.
E
- ECC (error-correcting code)
- Extra bits stored with data that let single-bit errors be corrected and double-bit errors detected. It is an option in BRAM, UltraRAM and DDR controllers, and interleaving protects it against multiple-bit upsets.
- ECO (engineering change order)
- A small, targeted edit to a placed and routed design, such as changing a LUT equation or rerouting one net, without a full rebuild. Used late in a project when a rerun would disturb timing.
- eFPGA (embedded FPGA)
- A block of programmable fabric licensed as IP and placed inside an ASIC or SoC, so parts of a fixed chip can be updated after manufacture. Achronix, Flex Logix, QuickLogic and Menta offer them.
- eFuse
- One-time-programmable bits blown by current, used to store keys, device identities and security settings permanently. Once an option such as encrypted-only loading is set, it cannot be undone.
- Emulation
- Running a design on dedicated hardware, usually a rack of large FPGAs, at kilohertz to megahertz speeds instead of simulating it. ASIC teams use it to bring up software before silicon arrives, where simulation would take weeks.
- Entity
- In VHDL, the declaration of a design unit's name, ports and generics, kept separate from its implementation. One entity can have several architectures.
- EOL (end of life)
- The point at which a vendor stops making a part, announced with a last-time-buy window. FPGA families typically stay in production for 15 years or more, so check the roadmap and lifetime before designing one into a long-lived product.
- Equalisation
- Compensating for frequency-dependent loss in a channel, using pre-emphasis at the transmitter and continuous-time or decision-feedback equalisers at the receiver. Transceivers expose adjustable settings for both.
- Equivalence checking
- Formally proving that two designs, such as the RTL and the post-synthesis netlist, behave identically. Used to confirm that synthesis or an ECO changed nothing it should not have.
- Ethernet MAC
- The media access control layer that frames packets, adds and checks CRCs and handles addresses. FPGAs offer hard MACs at 10 Gb/s to 400 Gb/s and soft ones for gigabit and below, each needing a PHY.
- Evaluation board
- A vendor or partner board carrying an FPGA with power, configuration flash, JTAG and a selection of interfaces, meant for learning or prototyping. Prices run from under 50 pounds to several thousand.
- Eye diagram
- An oscilloscope or transceiver view that overlays many bit periods so the open eye shows the timing and voltage margin. A closing eye means bit errors are on the way.
F
- F4PGA
- The umbrella project, formerly SymbiFlow, that aims to document the bitstreams of AMD 7 series and other devices and drive them with Yosys, VPR and nextpnr. Progress is slower than for the Lattice parts.
- False path
- A constraint telling STA to ignore a path that is never exercised or where timing is irrelevant, such as a static configuration register. Over-use hides real bugs, especially on clock domain crossings.
- Fault injection
- Deliberately glitching the clock, supply voltage or a laser spot to make a device skip a check or leak data. Secure boot code adds redundant checks and glitch detectors to resist it.
- FFT (fast Fourier transform)
- The efficient algorithm for converting N time samples into N frequency bins. FPGA cores stream it through pipelined radix-2 or radix-4 stages, which is why OFDM modems are built around them.
- FINN
- AMD's open-source framework for building dataflow accelerators from heavily quantised networks of 1 to 4 bits. Each layer becomes a streaming block sized to the required throughput.
- FIR filter
- A finite impulse response filter, a weighted sum of the last N input samples. It is always stable, has linear phase when symmetric, and maps directly onto DSP slices at one tap per multiply.
- Fixed-point arithmetic
- Representing fractional numbers as integers with an implied binary point, so maths uses plain integer multipliers and adders. It is the normal number format for FPGA DSP, with floating point reserved for where range matters more than area.
- Flip-flop
- An edge-triggered storage element that captures its D input on a clock edge and holds it until the next one. Modern fabrics pair each LUT with one or two, and a group sharing a clock is called a register.
- Floating and node-locked licences
- A node-locked licence is tied to one machine by its network address or a dongle. A floating licence is served from a shared server to whoever checks it out, limited by seat count, which suits teams and CI farms but fails when the server is unreachable.Hub: careers and industry. Related: Licence
- Floorplanning
- Constraining where parts of a design may be placed, usually with rectangular regions, to keep related logic together or near its pins. Most designs need none, while large or reconfigurable ones depend on it.
- fmax
- The highest clock frequency at which a design meets timing, derived from its most critical path. Tools report it per clock, and it changes with speed grade, voltage and temperature.
- Formal verification
- Proving properties of a design mathematically for all possible inputs rather than sampling with simulation. Tools such as SymbiYosys and JasperGold use SAT and SMT solvers to check assertions.
- FPGA (field-programmable gate array)
- A chip whose logic, memory and wiring are set after manufacture by loading a bitstream into configuration memory. The same silicon can be a video pipeline one week and a network switch the next.
G
- Gate level
- A design expressed as individual primitives and their wiring, as produced by synthesis or implementation. Gate-level simulation is slow but checks that the tools preserved the intended behaviour.
- Generate
- An HDL construct that creates hardware repeatedly or conditionally at elaboration time, driven by loops and parameters. It is how you build an array of identical channels without copying code.
- GHDL
- An open-source VHDL analyser and simulator supporting VHDL-2008, with a plugin that lets Yosys synthesise VHDL. It is the main free route for VHDL users.
- Gray code
- A binary ordering in which consecutive values differ in one bit, so a counter crossing clock domains can only be read as its old or new value. Dual-clock FIFO pointers use it.
H
- Handshake
- A protocol in which a request is held until an acknowledge returns and is then dropped. Used for multi-bit clock domain crossings at low rates and, as valid and ready, inside AXI4-Stream.
- Hard processor
- An Arm or RISC-V CPU built into the silicon beside the fabric, as in AMD Zynq, Altera SoC FPGAs and Microchip PolarFire SoC. Altera calls the block the hard processor system (HPS).
- HBM (high bandwidth memory)
- DRAM dies stacked beside the FPGA on an interposer, delivering hundreds of gigabytes per second over thousands of short connections. Found in large data-centre devices where DDR bandwidth runs out.
- HDMI
- The consumer video interface, carrying TMDS-encoded pixel data over three differential pairs plus a clock pair. Hobby boards drive 720p or 1080p from fabric I/O without needing a transceiver.
- HLS (high-level synthesis)
- Generating RTL from C, C++ or another high-level language, with pragmas steering the parallelism. Tools include Vitis HLS, Catapult and the open-source Bambu.
- hls4ml
- An open-source tool from the particle physics community that converts Keras and PyTorch models into HLS code for very low latency inference, often under a microsecond.
- Hold time
- The interval after the clock edge during which a flip-flop's D input must stay stable. Hold violations come from very short paths or large skew and cannot be fixed by slowing the clock.
I
- I/O bank
- A group of pins, typically 24 to 52, that share one supply voltage and reference. Every pin in a bank must use an I/O standard compatible with that voltage, such as LVCMOS18 or LVDS, which is the first constraint on pin planning.
- I/O delay constraint
- Input and output delay constraints that describe the external device's timing relative to the clock, so STA can check pin-to-register paths. Without them, interface timing is unverified.
- I2C
- A two-wire open-drain bus with clock and data, addressing up to 127 devices at 100 kHz to 3.4 MHz. Common for board management, EEPROMs and configuring sensors.
- Icarus Verilog
- A free event-driven Verilog simulator, slower than Verilator but able to handle delays, timing checks and most testbench constructs. The usual first simulator for hobby and teaching projects.
- IceStorm
- The project that reverse-engineered the Lattice iCE40 bitstream format in 2015, making the first fully open FPGA flow possible. It provides the device database and the icepack and iceprog tools.
- IIR filter
- An infinite impulse response filter that feeds previous outputs back, achieving a sharp response with few multipliers. The feedback loop makes it hard to pipeline and sensitive to fixed-point errors.
- Incremental compile
- Reusing the placement and routing of unchanged parts of a design from a previous run, so small edits compile faster and timing stays stable. AMD and Altera both support it from a reference checkpoint.
- Inference
- When synthesis recognises a hardware structure from behavioural code, such as a BRAM from an array with a clocked read, without an explicit primitive. It keeps code portable, but each tool has coding templates it expects.
- Initiation interval (II)
- The number of clock cycles between starting consecutive iterations of a pipelined loop or function. II=1 means a new input every clock, and the tool explains which dependency or memory port stops it achieving that.
- Instantiation
- Placing a named instance of a module, entity or primitive inside another design unit and connecting its ports. It is the alternative to inference for vendor-specific blocks.
- Interconnect (programmable routing)
- The grid of wire segments and switch boxes that joins logic tiles together, with every switch set by configuration memory. It typically accounts for more than half of an FPGA's delay and area.
- Interface (SystemVerilog)
- A SystemVerilog construct that bundles related signals, such as an AXI bus, into one port with modports that fix direction. It shortens port lists and keeps connections consistent.
- Interposer (2.5D integration)
- A silicon or organic layer beneath several dies that carries dense wiring between them, placing them side by side rather than stacked. AMD's stacked silicon interconnect brought it to FPGAs in 2011, and HBM is attached the same way.
- Interrupt
- A signal from logic to a processor asking for attention, routed through an interrupt controller and handled by a driver. The fabric of an SoC FPGA usually has a few dozen lines into the hard processor.
- IP (intellectual property)
- In FPGA usage, a licensed design block rather than a legal abstraction. Vendors bundle many cores with their tools, while third-party IP for PCIe, video codecs or memory controllers is bought per project or per unit.
- IP core
- A packaged, reusable block of logic delivered as RTL or an encrypted netlist, with parameters, a testbench and documentation. Vendors ship catalogues of them and third parties sell the rest.
J
- JESD204
- The serial interface standard for data converters, carrying ADC and DAC samples over transceiver lanes with deterministic latency. JESD204B is widespread and JESD204C adds 64b/66b encoding and higher lane rates.
- Jitter
- Cycle-to-cycle variation in when a clock edge arrives, caused by noise in oscillators, PLLs and power supplies. It shortens the usable clock period and matters most for transceivers and ADC sampling.
- JTAG
- The IEEE 1149.1 test port, four or five pins used to program FPGAs, read status, drive debug cores and run boundary scan. Every development board exposes it, often through an on-board USB adapter.
L
- LAB (logic array block)
- Altera's grouping of ten ALMs that share local interconnect, clock and control signals. It is the rough equivalent of an AMD CLB.
- Lead time
- The delay between ordering a part and receiving it, normally weeks, but stretched beyond a year during the 2021 to 2023 shortage. Check it before committing a design to a specific device.
- Licence
- The right to use a tool or an IP core under its terms. FPGA tools range from free editions covering smaller devices to annual subscriptions costing several thousand pounds per seat.
- Linting
- Static analysis of HDL for suspicious constructs, including width mismatches, incomplete sensitivity lists, unintended latches and unused signals. Verilator in lint-only mode and Verible are free options.
- LiteX
- A Python framework for assembling SoCs from a soft CPU, a Wishbone or AXI interconnect, memory controllers and peripherals, targeting dozens of boards across vendors. It is built on Migen, the predecessor of Amaranth.
- Loop unrolling
- Replicating a loop body so several iterations run in parallel hardware. Fully unrolling a 64-iteration loop creates 64 copies and needs the array it reads to be partitioned so the data arrives in parallel.
- LUT (look-up table)
- The basic logic element of an FPGA, a tiny memory whose address inputs are the logic inputs and whose stored bits form the truth table. A 6-input LUT holds 64 bits and can implement any Boolean function of its six inputs.
- LVDS (low-voltage differential signalling)
- A pair of wires carrying opposite polarities with a swing of about 350 mV, giving noise immunity at hundreds of Mb/s per pair. Used for cameras, displays and ADC interfaces, in contrast to single-ended LVCMOS pins.
M
- MAC (multiply-accumulate)
- Computing a times b plus c in one operation, the heart of filters and matrix maths. A DSP slice does one per clock, and a device's peak DSP performance is quoted in GMAC/s.
- Metastability
- The state a flip-flop enters when its input changes inside the setup or hold window, leaving the output at an intermediate level for an unpredictable time. It cannot be prevented, only made rare with synchronisers.
- MicroBlaze
- AMD's 32-bit soft processor, configurable from a tiny microcontroller to a cached pipeline with an MMU that runs Linux. A RISC-V variant, MicroBlaze V, is now offered alongside the original.
- MIPI CSI-2
- The camera serial interface used by most image sensors, running D-PHY or C-PHY lanes at several Gb/s each. Many FPGAs now receive it directly on fabric I/O without an external bridge.
- Module
- Verilog's design unit, combining the port list and the implementation in one construct. Modules are instantiated inside each other to build a hierarchy.
- MTBF (mean time between failures)
- For a synchroniser, how often a metastable value is expected to escape to downstream logic. Each extra flip-flop stage multiplies the figure enormously, taking it from hours to many years.
- Multicycle path
- A constraint allowing a path more than one clock period, valid only when a clock enable guarantees the data is sampled every N cycles. Both the setup and the hold multiplier must be set.
N
- NCO (numerically controlled oscillator)
- A phase accumulator that steps by a tuning word each clock, with a table or CORDIC converting phase to sine. Frequency resolution is the clock rate divided by 2 to the power of the accumulator width, and the same block is called direct digital synthesis (DDS).
- Netlist
- A description of a design as connected cells rather than behaviour, produced by synthesis. Post-synthesis netlists use generic cells, post-implementation netlists use placed and routed primitives.
- nextpnr
- The open-source placer and router that takes a Yosys netlist and a device database and produces a placed and routed design, which a packer turns into a bitstream. It supports iCE40, ECP5, Nexus, Gowin and more.
- Nios
- Altera's soft processor family. The original Nios II uses a proprietary instruction set, while Nios V is a RISC-V implementation that replaces it in new designs.
- Non-blocking assignment
- Verilog's <= assignment, which schedules the update for the end of the time step so all registers appear to change together on the clock edge. Use it for every clocked assignment.
- NRE (non-recurring engineering)
- The one-off cost of developing a product, as distinct from the cost per unit. FPGAs trade a higher unit price for near-zero NRE, while an ASIC's masks and tooling cost millions.
O
- OpenFPGA
- A framework that generates the fabric, bitstream format and CAD support of a custom FPGA or eFPGA from an architecture description. Used in research and for embedded FPGA cores.
- openFPGALoader
- A command-line tool that programs bitstreams into dozens of boards and devices through FTDI, DirtyJTAG and other adapters, replacing the vendor programmer in open flows.
- Overlay
- A fixed accelerator architecture loaded onto the FPGA once and then driven by software, like a small domain-specific processor. It avoids a synthesis run per model at some cost in efficiency.
P
- Package
- A named collection of types, constants and functions shared across design units, available in both VHDL and SystemVerilog. Put bus widths and record types in one so every module agrees.
- Parameter (generic)
- A compile-time constant on a Verilog module (parameter) or VHDL entity (generic) that sets widths, depths or options when the unit is instantiated. Parameterised code is reused instead of rewritten.
- Partial reconfiguration
- Replacing the logic in one region of a running FPGA with a new partial bitstream while the rest keeps operating. Useful for swapping accelerators or radio waveforms without a reboot.
- Pblock
- AMD's name for a rectangular floorplanning region to which a set of cells is constrained. Partial reconfiguration requires each reconfigurable module to live in its own pblock.
- PCIe (PCI Express)
- The serial bus that links FPGA accelerator cards to a host CPU. Each lane runs at 8 Gb/s in Gen3 and 32 Gb/s in Gen5, and a hard block in the device handles the protocol.
- PHY
- The physical-layer circuit that converts between a MAC's digital interface and the actual electrical or optical signal. For gigabit Ethernet it is usually an external chip linked over RGMII or SGMII.
- Pipelining
- Breaking a long combinational path into stages separated by registers, so each stage fits in one clock period at the cost of latency. It is the main tool for raising fmax, and in HLS it lets a loop start a new iteration before the previous one finishes.
- Place and route
- The implementation stage after synthesis that produces a fully placed and routed netlist ready for bitstream generation. AMD calls it implementation and Altera calls it the fitter.
- Placement
- Choosing a physical location for every cell in the netlist, trading wire length against timing. A poor placement cannot be rescued by routing.
- PLL (phase-locked loop)
- A hard block that generates clocks at multiples or fractions of an input clock and aligns their phase. AMD's MMCM is a more capable variant with fine phase shifting and fractional division.
- Polyphase filter
- A filter split into sub-filters that each handle one phase of a rate change, so no multiplies are spent on samples that will be discarded. It is the efficient form of a decimating or interpolating FIR.
- Post-route simulation
- Simulating the fully implemented netlist with back-annotated delays. It is slow and rarely needed when STA is clean, but it catches missing constraints and reset problems.
- Power estimation
- Predicting a design's consumption from resource use, clock rates and toggle rates, with spreadsheet tools before implementation and simulation-based analysis after. Early estimates can be off by a factor of two, and the result sets the thermal design power the board must dissipate.
- PQC (post-quantum cryptography)
- Signature and key-exchange algorithms such as ML-DSA, ML-KEM and LMS that are designed to resist quantum computers. New devices are adding them for bitstream and boot authentication.
- Pragma
- A directive in HLS source code that controls how it becomes hardware, such as pipelining a loop or partitioning an array across memories. The same code gives very different hardware depending on them.
- Primitive
- A leaf cell in the vendor library that maps directly onto silicon, such as a BUFG, a LUT6 or an Altera altsyncram. Instantiating primitives gives control at the cost of portability.
- Process
- VHDL's procedural block and the counterpart of a Verilog always block. Its statements run in sequence when a signal in its sensitivity list changes, and a process with a rising_edge test describes registers.
- Project Apicula
- The documentation of Gowin bitstreams that lets Yosys and nextpnr target the GW1N and GW2A families found on the Tang boards.
- Project Trellis
- The documentation and tools for the Lattice ECP5 bitstream that enable nextpnr-ecp5. Project Oxide does the same job for the Lattice Nexus family.
- Propagation delay
- The time for a change at a cell's input to reach its output, including the routing after it. STA sums these delays along every path, and each LUT level costs roughly 0.1 to 0.3 ns plus wiring.
- Pruning
- Removing weights or whole channels that contribute little, leaving a smaller or sparser network. Structured pruning shrinks the hardware directly, while unstructured pruning only pays off on hardware that skips zeros.
- PS and PL
- AMD's terms for the two halves of a Zynq device, the processing system (hard CPU, memory controller and peripherals) and the programmable logic (fabric). They talk through AXI ports with a fixed memory map.
- PUF (physically unclonable function)
- A circuit that derives a device-unique key from manufacturing variation, so no key is ever stored where it could be read. Microchip and AMD devices use one to wrap other keys.
Q
- Q format
- A notation for fixed-point formats, so Q1.15 means one integer bit and 15 fractional bits in a 16-bit word. Writing it on every signal name avoids most scaling bugs.
- Quantisation
- Reducing the numeric precision of a model's weights and activations, typically from 32-bit floating point to 8-bit (INT8) or smaller integers. It cuts memory and multiplier cost sharply with little accuracy loss when calibrated well.
R
- Radiation hardened
- A device made immune or resistant to upsets and latch-up by design, through hardened flip-flops, process choices or antifuse configuration. It is expensive and usually several generations behind commercial silicon.
- Radiation tolerant
- A device characterised for radiation and expected to survive it with mitigation such as TMR and scrubbing, but built on a commercial process. Cheaper and faster than radiation-hardened parts.
- Reset synchroniser
- A circuit that asserts a reset at once but releases it in step with the clock, so every flip-flop leaves reset in the same cycle. Needed whenever the reset source is asynchronous.
- Retiming
- A synthesis optimisation that moves registers across logic to balance delays along a pipeline without changing behaviour. It works best when you have added spare registers at the ends of a long combinational block.
- RISC-V
- An open instruction set architecture with no licence fee, now the default choice for new soft processors and increasingly for hard ones. Dozens of open cores exist, from 1,000-LUT microcontrollers to Linux-capable designs.
- Root of trust
- The hardware trusted without further proof, typically a boot ROM, a key store and a cryptographic engine, from which all other trust in the system is derived.
- Rounding and truncation
- Ways of dropping low bits to shorten a word. Truncation discards them and introduces a bias, while rounding adds half a least significant bit first, and convergent rounding removes the remaining bias at the cost of an adder.
- Routing
- Assigning each connection in the placed design to physical wire segments and switches in the interconnect. It fails when demand exceeds the channels available, which the tools report as congestion.
- RTL (register-transfer level)
- A style of HDL that says which registers exist and what logic sits between them, without choosing specific gates. It is the input to synthesis and the level at which most design and simulation happens.
S
- Saturation
- Clamping a result to the largest or smallest representable value instead of letting it wrap around. It costs a comparator and turns a catastrophic overflow into mild distortion.
- Scrubbing
- Continuously reading configuration memory back, checking it against a known-good copy or CRC, and rewriting any corrupted frame. It limits how long an upset in the configuration can persist.
- SDC (Synopsys Design Constraints)
- The industry format for timing constraints, with commands such as create_clock and set_input_delay, used by Altera, Lattice, Microchip and the open-source tools. XDC is a superset of it.
- SDR (software-defined radio)
- Doing modulation, filtering and demodulation in programmable logic or software rather than analogue circuits, working on in-phase and quadrature (I/Q) sample pairs. The FPGA sits between the data converters and the processor in most SDR platforms.
- Secure boot
- A chain in which each boot stage verifies the next before running it, starting from immutable ROM and keys in eFuse. It breaks if any stage, including the bitstream, goes unsigned.
- Self-checking testbench
- A testbench that compares outputs against expected values and reports pass or fail by itself, so nobody has to read waveforms. It needs a reference model or golden data, and it is what makes regression runs possible.
- Sensitivity list
- The list of signals that wake a process or always block. A missing signal makes simulation and synthesis disagree, which is why always @* and process(all) exist.
- SerDes (serialiser/deserialiser)
- Logic that converts parallel data to a fast serial stream and back again. Fabric I/O can run DDR SerDes to about 1.6 Gb/s per pin, and dedicated transceivers go far faster.
- Setup time
- The interval before the clock edge during which a flip-flop's D input must be stable. A setup violation means data arrived too late, and the fix is a faster path or a slower clock.
- SEU (single-event upset)
- A bit flipped by an ionising particle in a flip-flop, memory or configuration cell. In an SRAM FPGA a configuration upset changes the circuit itself until it is scrubbed, and one particle flipping several neighbouring bits is a multiple-bit upset (MBU).
- Side channel
- Leakage of secret information through physical effects such as power draw, electromagnetic emission or timing. A correctly implemented cipher can still give away its key this way.
- Signal integrity
- Keeping digital signals clean on a board by controlling reflections, crosstalk, ground bounce and loss. It matters for DDR, LVDS and anything above about 100 MHz, and vendors publish IBIS models so it can be simulated.
- Single-event effects (SET, SEL, SEFI)
- The family of faults caused by one particle strike. A single-event transient (SET) is a brief pulse in logic, a single-event latch-up (SEL) is a high-current state that needs a power cycle, and a single-event functional interrupt (SEFI) halts a control block such as the configuration engine.
- Slack
- The margin by which a timing path meets its requirement, computed as required time minus arrival time. Positive slack passes, negative slack fails, and the path with least slack sets fmax.
- Soft processor
- A CPU implemented in the fabric from LUTs and BRAM, such as MicroBlaze, Nios V, NEORV32 or VexRiscv. Slower than a hard core but available in any device and configurable down to a few thousand LUTs.
- Speed grade
- A suffix in the part number that says how fast the silicon was binned, such as -1 (slowest) to -3 for AMD or C6 to C8 for Altera. Faster grades cost more and the timing models differ, so set it before running STA.
- SPI (serial peripheral interface)
- A synchronous bus with clock, data in, data out and chip select, used for flash, sensors and ADCs at up to tens of MHz. The configuration flash of most FPGAs speaks a quad-SPI variant.
- SpinalHDL
- A Scala-based hardware description language with strong typing and a rich bus library, best known for the VexRiscv and NaxRiscv processors. It generates Verilog or VHDL.
- STA (static timing analysis)
- Checking every register-to-register and I/O path against setup and hold requirements using delay models, without running a simulation. It is exhaustive, but only as good as the constraints it is given, and its output is the timing report.
- Static power
- Power consumed while the device is idle, mainly transistor leakage in the fabric and configuration memory. It rises steeply with temperature and with smaller process nodes.
- Structured ASIC
- A pre-fabricated base wafer customised with a few metal layers, offering a middle path between FPGA flexibility and ASIC unit cost. Altera's eASIC is the main current example.
- Synchroniser
- Two or more flip-flops in series clocked by the receiving domain, giving a metastable first stage time to settle. It is the standard way to carry a single bit across clock domains.
- Synchronous reset
- A reset sampled on the clock edge like any other input, so it needs a running clock but has no release timing problem. It is the default on AMD devices and in this site's examples.
- Synthesis
- Turning RTL into a netlist of logic cells, with optimisations such as constant propagation and state machine re-encoding along the way. It is the first step of the flow and where inference decisions are made.Hub: timing and constraints. Related: Technology mapping, Netlist, RTL (register-transfer level), Inference
- Synthesisable subset
- The part of an HDL that synthesis tools can turn into hardware. File I/O, time delays, most initial blocks and object-oriented features are for simulation only.
- SystemVerilog
- The IEEE 1800 superset of Verilog that adds the logic type, interfaces, packages, assertions and object-oriented testbench features. Synthesis tools support a growing subset, while simulators support nearly all of it.
- Systolic array
- A grid of processing elements that pass partial results to their neighbours every clock, so data flows through with no shared memory. It is the common structure for matrix multiplication in FPGA and AI accelerators.
T
- Technology mapping
- The synthesis step that converts generic gates into the target device's real cells, packing logic into LUTs of the right size and recognising carry chains and memories. Yosys delegates it to the ABC library.
- Temperature grade
- The operating range a part is qualified for, from commercial (0 to 85 °C junction) through extended and industrial (-40 to 100 °C) to automotive (AEC-Q100) and military. Industrial parts cost more and may offer fewer speed grades.
- Testbench
- A non-synthesisable HDL or Python module that instantiates the design under test, drives stimulus into it and checks what comes out. Every design should have one before it reaches a board.Hub: verification. Related: DUT (device under test), Self-checking testbench, cocotb, VCD (value change dump)
- Throughput versus latency
- Throughput is how much work completes per second, latency is how long one item takes. Batching raises throughput and latency together, which is why FPGAs win in low-latency, small-batch inference against GPUs.
- TID (total ionising dose)
- The cumulative radiation absorbed over a mission, measured in krad or Gy, which gradually shifts transistor thresholds and raises leakage. It is a separate concern from single-event effects.
- TMR (triple modular redundancy)
- Three copies of a circuit with majority voting on the outputs, so one upset is outvoted. It costs more than three times the area and needs voters inside feedback loops to be effective.
- TNS (total negative slack)
- The sum of every failing endpoint's negative slack. A large TNS with a small WNS points to a widespread problem such as an over-ambitious clock period rather than one bad path.
- Transceiver
- A hard multi-gigabit serial block with its own PLL, clock and data recovery, equalisation and encoding, running from a few Gb/s to over 100 Gb/s per lane. PCIe, Ethernet and JESD204 all sit on top of one.Hub: high speed io. Related: SerDes (serialiser/deserialiser), Equalisation, PCIe (PCI Express), Eye diagram
- TRNG (true random number generator)
- A source of randomness from physical noise such as ring oscillator jitter, needed for keys and nonces. Unlike a pseudo-random generator it cannot be replayed from a seed.
U
- U-Boot
- The open-source second-stage bootloader used on nearly every Linux-capable SoC FPGA. It loads the kernel and device tree from flash, SD card or network and hands over.
- UART
- An asynchronous serial link with start and stop bits and no clock line, typically at 115,200 baud over a USB bridge. It is the first peripheral most people build and the usual console for a soft processor.
- UVM (Universal Verification Methodology)
- The SystemVerilog class library, standardised as IEEE 1800.2, for building reusable constrained-random testbenches from agents, sequences and scoreboards. Heavy for small FPGA projects, standard in ASIC teams.
V
- VCD (value change dump)
- The plain-text waveform format from IEEE 1364 that every simulator can write and viewers such as GTKWave and Surfer can read. Files grow quickly, so compressed formats such as FST are common with Verilator and Icarus.
- Verilator
- An open-source tool that compiles synthesisable Verilog and SystemVerilog into a C++ model, giving cycle-based simulation far faster than event-driven simulators. It does not model delays or most X values.
- Verilog
- A C-like hardware description language standardised as IEEE 1364 and widely used in industry and open-source tools. Verilog-2001 remains the common denominator that every tool accepts.
- VHDL
- A strongly typed hardware description language standardised as IEEE 1076, with Ada-like syntax. Common in European, defence and aerospace work, and the 2008 revision adds useful features such as unconstrained records.
W
- Wishbone
- An open, royalty-free bus specification favoured by open-source cores and by LiteX. It is simpler than AXI, with a classic single-cycle handshake or a pipelined mode.
- WNS (worst negative slack)
- The most negative setup slack of any path in the design. Timing is met when WNS is zero or positive, and the path that sets it is the one to fix first.
X
- XDC (Xilinx Design Constraints)
- AMD's constraint file format for Vivado, built on Tcl and SDC timing commands plus physical commands for pins, I/O standards and placement. Constraints apply in file order, so order matters.
Y
- Yocto
- A build system for custom embedded Linux distributions that assembles kernel, bootloader and root filesystem from recipes. AMD's PetaLinux is a wrapper around it, and Altera and Microchip provide board support layers for it.
- Yosys
- The open-source synthesis framework that reads Verilog (and VHDL through GHDL) and produces netlists for iCE40, ECP5, Gowin and other devices, or generic cells for ASIC flows. It calls the ABC library for logic optimisation and LUT mapping.