What is an FPGA?

This lesson is for anyone who has heard the term FPGA and wants a clear mental model before touching a tool or a line of HDL. By the end you should be able to say what an FPGA is, what it is not, and why a working engineer would pick one over a microcontroller or a custom chip.

A chip you wire up yourself

A field-programmable gate array (FPGA) is an integrated circuit that contains a large number of small logic blocks, a large amount of configurable wiring between them, and a set of switches that decide which wires connect to which. When you “program” an FPGA you are not loading instructions for a processor to execute. You are setting those switches so that the chip becomes the circuit you described.

That distinction is the whole subject. A microcontroller is a fixed circuit that reads a program. An FPGA is a blank sheet of logic that becomes your circuit. The word “field” means the configuration happens where the chip is used, on your bench or in the product, rather than in the factory.

A typical mid-range device today has somewhere between 20,000 and 1,000,000 logic cells, a few megabits of on-chip memory, a few hundred hardware multipliers and several hundred input/output pins. A small device aimed at low-power work might have 1,280 logic cells and 80 kb of memory. The range is wide, but the structure is the same.

FPGA, microcontroller, ASIC, GPU

Four kinds of chip are regularly compared, and each solves a different problem. The table gives the short version.

	Microcontroller (MCU)	FPGA	ASIC	GPU
What runs	A sequence of instructions	A circuit you describe	A circuit the designer froze in silicon	Thousands of small processors running the same instruction stream
How parallel	One or a few cores	As parallel as your design (thousands of independent operations per clock)	Whatever was built	Massively parallel, but in lock-step groups
Change the function later	Yes, reload firmware	Yes, reload the bitstream	No	Yes, reload software
Latency of a response	Microseconds, depends on software	Tens of nanoseconds, deterministic	Nanoseconds	Microseconds to milliseconds
Unit cost at low volume	Pennies to a few pounds	A few pounds to a few thousand pounds	Millions in up-front cost, pennies per part after	Tens to thousands of pounds
Power for a given job	Low for simple tasks	Moderate	Lowest	High
Skill needed	C or Python	Hardware description languages and timing	Full chip design team	CUDA, OpenCL or a framework

A microcontroller is the right default for most embedded work. It is cheap, well understood, and most tasks do not need more. You reach for an FPGA when the task needs many things to happen at the same time, with precise timing, or when the data rate is higher than a processor can keep up with. An ASIC (application-specific integrated circuit) is what you build when the volume is large enough to pay for custom silicon, often tens of millions of pounds for a modern process. Many ASICs start life as FPGA prototypes. A GPU is a processor built for arithmetic on large arrays, and it wins when the problem is wide arithmetic with no hard latency bound.

Where FPGAs are used

FPGAs appear wherever one of three conditions holds: the interface is too fast for software, the timing must be exact, or the function must change after the product ships. Some concrete cases, each of which you will meet again in later tracks:

• Wired and wireless communications equipment, where a device receives data at 10 Gb/s to 400 Gb/s per lane and must process every bit without dropping any.
• Test and measurement instruments such as oscilloscopes and logic analysers, where the front end samples at gigahertz rates and the logic must capture, trigger and filter in hardware.
• Motor control and power electronics, where a control loop closes in under a microsecond and a jitter of a few nanoseconds matters.
• Video and imaging pipelines, where several camera streams need to be corrected, scaled and compressed in real time.
• Data centre acceleration, where an FPGA sits beside a server CPU and handles network packet processing, compression, encryption or database filtering.
• Space, defence and high-reliability systems, where the ability to fix a design after launch, and to choose radiation-tolerant parts, outweighs the cost.
• Prototyping ASICs, where a design is proven on one or more large FPGAs before anyone pays for a mask set.

An FPGA is usually the wrong choice for a user interface, a web server, a file system or anything else that is mostly sequential decision-making. Those are processor jobs. Many modern FPGAs include a hard processor on the same die (an SoC FPGA) precisely so that you can put the sequential part on the processor and the parallel part in the fabric. The SoC FPGAs topic covers that family.

The fabric at a glance

Vendors call the programmable part of the chip the fabric. The diagram shows the pieces you will find in almost every device. The proportions vary, the names vary by vendor, but the kinds of block are stable.

Logic blocks

The bulk of the area is a grid of small, identical logic blocks. AMD calls them configurable logic blocks (CLBs), Altera calls them logic array blocks, Lattice calls them programmable logic blocks. Each one contains a handful of look-up tables (LUTs) and flip-flops. A LUT is a tiny memory that implements any Boolean function of its inputs, and a flip-flop stores one bit between clock edges. A 6-input LUT holds 64 bits of configuration and can be any one of the 18 quintillion possible 6-input functions. Lesson 03 goes into the LUT in detail and lesson 04 covers the flip-flop.

Routing

Between the logic blocks runs a dense network of wires with programmable switches at the crossings. In most devices the routing takes more silicon than the logic. The tools decide which switches close so that the output of one LUT reaches the input of another, and the path they choose sets how fast your design can run. Routing is invisible in your source code but it dominates timing and it is why place and route takes minutes or hours.

Block RAM

Columns of dedicated memory blocks, usually 18 kb or 36 kb each at AMD, 20 kb at Altera, 4 kb or larger at Lattice, provide fast on-chip storage. A mid-range device carries a few megabits in total. Each block can be configured as a single- or dual-port RAM, a ROM or a FIFO. Lesson 09 covers memories.

DSP blocks

Dedicated multiplier-accumulator units sit in their own columns. A typical block multiplies an 18-bit by a 25-bit number (AMD) or two 18-bit numbers (Altera, Lattice) and adds the result to a 48-bit accumulator, every clock cycle. A device with 240 DSP blocks at 400 MHz performs 96 billion multiply-accumulates per second. Building the same multipliers from LUTs would be far slower and larger.

I/O and transceivers

The ring of input/output blocks around the edge drives and receives signals at configurable voltage standards, from 1.2 V to 3.3 V, single-ended or differential. Larger devices also carry high-speed serial transceivers for PCIe, Ethernet and similar links at 10 Gb/s and beyond.

Clocking and configuration

Clock management blocks (PLLs and similar) multiply, divide and phase-shift incoming clocks and distribute them on dedicated low-skew networks. A small block of configuration logic loads the bitstream into the configuration memory at power-up. Lesson 02 explains how that happens.

What “programmable” really means

The word causes most beginner confusion, so it deserves a careful statement.

In an FPGA, every LUT’s truth table, every flip-flop’s mode, every routing switch and every I/O setting is held in configuration memory. In most devices that memory is static RAM, one bit per switch. A device with a few million configuration bits is ordinary. The file that fills that memory is the bitstream.

When the bitstream is loaded, the chip becomes the circuit. Nothing is executing. There is no instruction pointer and no fetch-decode-execute cycle. If your design has 2,000 adders, then 2,000 physical adders exist in the fabric at once and all of them add on every clock edge, whether or not their results are used. Change the bitstream and the chip becomes a different circuit.

Three consequences follow:

1. Time in your design is measured in clock cycles, and every part of the circuit advances together on each cycle. A processor’s idea of “do this, then that” does not exist unless you build a state machine to create it. Lesson 07 shows how.
2. Resources are physical. Using more logic means using more of the chip. When the chip is full, it is full. A processor can run a longer program in the same memory. An FPGA cannot run a bigger circuit in the same fabric.
3. The description you write is of hardware, not of a sequence of steps. The languages, Verilog and VHDL, look like software and that is the trap. Lesson 05 is where you start writing them with the right picture in mind.

A quick sense of scale

Some numbers make the abstractions concrete. All are typical rather than exact and will drift over time.

• A small Lattice iCE40 UltraPlus has 5,280 LUTs, 1 Mb of RAM, 8 multipliers and consumes under 100 µW in standby. It fits in a 2.15 mm by 2.55 mm package.
• A mid-range AMD Artix 7 on a student board like the Basys 3 has 33,280 logic cells, 1.8 Mb of block RAM, 90 DSP slices and runs most beginner designs at 100 MHz.
• A large AMD Versal or Altera Agilex device has millions of logic cells, hundreds of megabits of memory, thousands of DSP engines, and costs more than a small car.

The beginner track uses the small and mid-range parts. The concepts transfer upward unchanged.

Exercise

Without looking anything up, classify each of the following as best suited to a microcontroller, an FPGA, an ASIC or a GPU, and write one sentence for each explaining why. Then check your answers against the table above.

1. The controller inside a washing machine.
2. A device that captures eight 4K video streams, stitches them into one panorama and outputs it with under 10 ms of delay.
3. The radio baseband chip inside a smartphone that will ship 50 million units.
4. Training a large image-recognition model from a dataset of ten million pictures.
5. A circuit that measures the time between two laser pulses to a resolution of 100 ps.

For a second exercise, find the datasheet summary page for any FPGA you have heard of and locate four numbers: the number of logic cells or LUTs, the total block RAM, the number of DSP blocks and the number of user I/O pins. Write them down with units. You will need the habit of reading these tables for the rest of this track.

Summary

• An FPGA is a chip whose logic blocks and wiring are set by a configuration file, so it becomes the circuit you describe rather than executing instructions.
• It differs from a microcontroller (sequential, cheap, easy), an ASIC (fixed, cheapest at volume, fastest) and a GPU (wide arithmetic, high power) by offering reprogrammable parallel hardware with deterministic timing.
• The fabric is made of LUT-and-flip-flop logic blocks, programmable routing, block RAM, DSP blocks, I/O blocks and clock management.
• “Programmable” means the configuration memory is loaded in the field. Nothing executes. Everything in the design exists at once and advances every clock cycle.
• FPGAs suit high data rates, exact timing and functions that must change after shipping. They are a poor fit for sequential, decision-heavy tasks.

Further reading

• AMD UG474, 7 Series FPGAs Configurable Logic Block User Guide: the definitive description of one vendor’s logic block, readable once you have finished lesson 03.
• AMD UG470, 7 Series FPGAs Configuration User Guide: how a bitstream gets into the chip, which lesson 02 summarises.
• Lattice iCE40 family page: datasheets for the small devices used in many open-source projects.
• Yosys manual: the open-source synthesis tool, whose documentation explains what synthesis produces from your description.