eFPGA and adaptive ASICs
Embedded FPGA IP from Achronix, Menta, QuickLogic and Flex Logix, when a block of programmable logic belongs in an SoC, and the structured-ASIC and chiplet paths between an FPGA and a full custom chip.
Overview
An embedded FPGA (eFPGA) is a block of look-up tables, routing and sometimes block RAM and DSP delivered as IP, to be placed inside someone else’s ASIC or SoC. The chip is fixed, but one region of it can be reprogrammed after tape-out. This hub is for architects deciding whether that region is worth its area, and for FPGA engineers who find themselves targeting one. It also covers the opposite move: starting from an FPGA design and migrating it, wholly or partly, to a structured ASIC or chiplet when volume justifies it.
The pitch for eFPGA is a narrow one. An ASIC is cheapest per unit and fastest, but it cannot change. An FPGA changes freely but costs more per unit, draws more power, and sits outside the SoC behind an interface. An eFPGA puts a few percent of programmable area where the uncertainty is, with the rest of the chip hard. Whether that is worth it depends on how certain you are about what will need to change.
Key ideas
When to embed programmable logic
The cases that have shipped share a pattern. The programmable region implements something that is specified late, varies by customer or standard, or must be updated in the field: a packet parser for protocols not yet finalised, a sensor interface in a product sold to many camera vendors, a cryptographic agility block, a radio filter that must track regulation, or a hardware accelerator whose algorithm the company expects to tune after launch. Defence and aerospace use eFPGA to keep a sensitive algorithm out of the mask set entirely. The cases that fail are the ones where the region was added as insurance without a known use, because an idle eFPGA is the most expensive silicon on the die. An eFPGA tile is roughly 20 to 40 times the area of equivalent hard logic and runs at perhaps a third of the clock rate, so the question is never “could this be programmable” but “what would we change, and what does it cost to tape out again instead”.
Who sells it and how it is delivered
Achronix Speedcore is delivered as a hard macro for a specific process (TSMC 16 nm and 7 nm among others), with the customer choosing the mix of LUT, RAM, DSP and machine-learning tiles, and the same ACE tools used for Achronix’s own Speedster chips. Flex Logix EFLX is built from tiles of a few thousand LUTs that abut to form larger arrays, offered on a range of nodes from 180 nm to 7 nm, and has been licensed into defence and automotive programmes. QuickLogic ArcticPro grew out of the company’s own low-power FPGAs and is positioned for small arrays on mature nodes, with an open-source tool flow (Yosys and VPR through the company’s Aurora tools) as a selling point. Menta, in France, delivers a soft eFPGA described in RTL, which any foundry’s standard-cell flow can synthesise, at some cost in density. Beyond those, the OpenFPGA project generates a fabric and its bitstream tools from a description file, which is how several academic and some commercial chips got their programmable regions. In every case the eFPGA vendor provides the fabric, the bitstream tools and the configuration interface, and the SoC team provides the clocks, power domains and the AXI or custom bus to connect it.
The other direction: FPGA to ASIC
An FPGA design that reaches volume can move to a cheaper platform in steps. Structured ASICs are the shortest step. Altera’s eASIC devices (the N5X family at the time of writing) are built from pre-fabricated arrays of logic and memory, customised by a few metal layers, so a Stratix 10 or Agilex design migrates with a modest non-recurring cost, a fraction of the FPGA’s power and no change to the pin-out in some packages. Full-custom conversion through a design house replaces the FPGA with a standard-cell ASIC for the lowest unit cost and the highest NRE. Chiplets are the newest option: a hard chiplet for the fixed logic and an FPGA chiplet (AMD and Altera both build their large devices this way internally) sharing a package over a die-to-die link such as UCIe. Whichever path, design the RTL from the start to be portable: avoid vendor primitives where an inferred structure will do, keep clock domain crossings explicit, and keep the memories behind wrappers.
Where to start
An eFPGA is an FPGA without the chip around it, so the beginner track applies unchanged. /learn/beginner/01-what-is-an-fpga/ and /learn/beginner/03-combinational-logic-and-luts/ explain the fabric that is being embedded, and /learn/beginner/02-how-an-fpga-is-programmed/ covers the configuration mechanism the host CPU will drive. The /topics/fpga-architecture/ hub explains what a tile is, and /topics/soc-fpgas/ covers the processor-to-fabric interfaces that an eFPGA reuses. To experiment, OpenFPGA with Yosys and VPR will generate a small fabric you can simulate. An expert track on silicon integration is coming.
Tools and vendors
| Vendor | Product | Delivery | Nodes | Tools |
|---|---|---|---|---|
| Achronix | Speedcore | Hard macro, custom tile mix | 16 nm, 7 nm, others on request | ACE (same as Speedster) |
| Flex Logix | EFLX | Abutting hard tiles | 180 nm to 7 nm | EFLX compiler |
| QuickLogic | ArcticPro, Australis | Hard, generated per node | 180 nm to 12 nm at the time of writing | Aurora (Yosys and VPR based) |
| Menta | eFPGA IP | Soft RTL, synthesised by customer | Any | Origami |
| OpenFPGA (open source) | generated fabric | RTL plus bitstream generator | Any | Yosys, VPR |
| Altera | eASIC N5X | Structured ASIC, FPGA migration | 16 nm | Quartus Prime Pro migration flow |
Hard eFPGA IP comes with per-node licence fees and royalties and a qualification lead time, so the decision is made at architecture time, not at RTL time.
Common mistakes
- Adding an eFPGA region without a named first use and a named owner for its bitstreams.
- Underestimating the area. Compare the eFPGA tile against hard logic at the clock rate the hard logic would run.
- Forgetting the configuration path, including how a bitstream is authenticated and loaded securely at boot.
- Clocking the eFPGA from the SoC’s fastest domain and expecting closure. Budget for a third of the hard clock.
- Writing FPGA RTL for a device that will later migrate to eASIC or an ASIC with vendor-specific primitives everywhere.
- Treating a structured ASIC as free of verification. The metal-layer customisation needs the same sign-off as any tape-out.
Going deeper
- Achronix Speedcore eFPGA, with the tile options and process list.
- Flex Logix EFLX documentation, now distributed through Analog Devices after the 2024 acquisition; the standalone site was offline at the time of writing.
- QuickLogic eFPGA, including the open-source tooling notes.
- Menta, the soft eFPGA vendor.
- OpenFPGA, with the documentation for generating and programming a fabric.
- UCIe consortium, for the chiplet interconnect specification.