Careers and industry
How the FPGA industry is structured, what the main engineering roles do, the skills and interview topics that matter, how to build a portfolio, and what pay looks like in broad bands.
Overview
FPGA engineering is a small profession inside electronics, numbering in the low hundreds of thousands worldwide at a generous count, with demand that has outrun supply for most of the past decade. This hub is for students deciding whether to specialise, engineers moving in from software or ASIC design, and working FPGA engineers thinking about the next role. It describes the industry’s shape, the roles, the skills employers test for, and the ways to show those skills before you have a job title.
The industry at the time of writing is two large device vendors (AMD, which bought Xilinx in 2022, and Altera, spun back out of Intel in 2024 and 2025), one mid-size (Microchip), a group of smaller ones (Lattice, Efinix, Gowin, QuickLogic, Achronix, NanoXplore, Renesas and several in China), the EDA companies whose tools they all depend on (Siemens, Synopsys, Cadence, plus the open-source projects), and the far larger population of companies that use the devices. Market estimates for FPGA sales vary by analyst but cluster around 10 to 15 billion USD a year, with communications, data centre, industrial, automotive, aerospace and defence, and test and measurement as the main segments. The users employ most of the engineers.
Key ideas
The roles
RTL design engineer: writes and owns the hardware. Verilog, SystemVerilog or VHDL, timing closure, clock domain crossing, resource optimisation, integration of vendor IP. The core role and the one most people mean by “FPGA engineer”.
Verification engineer: proves the RTL does what the specification says. SystemVerilog and UVM in larger teams, cocotb and formal in smaller or newer ones. Often paid as well as or better than design, and in shorter supply.
FPGA application engineer (FAE): works for a vendor or distributor, helps customers choose and use the devices, reproduces their problems, runs training. A good route for people who like variety and talking to people, and a common path into product marketing or management.
DSP and communications engineer: designs filters, modems, radar and beamforming chains in fixed-point arithmetic, usually with MATLAB or Python models first. The maths matters more than the HDL.
Embedded and SoC engineer: builds the processor side of SoC FPGAs, device drivers, Linux bring-up, firmware that talks to the fabric. Many enter from embedded software.
Systems and board engineer: schematics, power, signal integrity, pin planning. Adjacent to FPGA work and often the same person on small teams.
What interviews test
Interviews for design roles are consistent across companies. Expect to draw a circuit for a problem (a clock divider, an edge detector, a FIFO with its full and empty logic, a two-flop synchroniser and why it works), to explain setup and hold and what to do when timing fails, to describe a clock domain crossing for a multi-bit value, to write a small module on a whiteboard without a simulator, and to talk through a design you have built end to end, including the bugs. Verification interviews add constrained random, coverage and the structure of a UVM environment. DSP interviews add quantisation, overflow and filter structures. Vendor FAE interviews add product knowledge and a presentation. Certifications exist (AMD and Altera both run training programmes with certificates, as do some universities) but employers weight them lightly next to a project you can explain and a GitHub repository they can read.
Building a portfolio and reading the pay bands
Two or three finished projects on a cheap board, each with a readme, a testbench, a timing report and a short write-up of what went wrong, demonstrate more than a degree module. Good candidates: a UART with a proper testbench, a VGA or HDMI pattern generator, a RISC-V soft core running C, a small DSP chain with a Python golden model, or a contribution to an open-source core such as LiteX, NEORV32 or a nextpnr architecture. Pay varies by region more than by anything else, and these are broad bands only. Graduate roles start at the lower end of the local engineering scale. Experienced design and verification engineers earn above the median for electronics, and senior specialists in finance, data centre and defence sit well above it. Contract rates in the UK, Europe and North America are high relative to permanent pay because supply is thin. Vendor FAE pay is comparable to design roles with better travel. Treat any specific number you read online as a snapshot of one market in one year.
Where to start
Complete the beginner track end to end, from /learn/beginner/01-what-is-an-fpga/ to /learn/beginner/10-from-rtl-to-board/, with the exercises done on a real board. /learn/beginner/06-simulation-and-testbenches/ and /learn/beginner/07-finite-state-machines/ cover the two things most often asked in interviews. Then pick one project from the list above and finish it, including the write-up. The intermediate and advanced tracks, which cover the timing, verification and SoC skills that separate junior and senior roles, are coming.
Tools and vendors
| Employer type | Examples | What they hire for |
|---|---|---|
| Device vendors | AMD, Altera, Microchip, Lattice, Efinix | FAEs, IP designers, tool developers, silicon architects |
| EDA and IP | Siemens, Synopsys, Cadence, YosysHQ, IP houses | Tool developers, verification, IP design |
| Communications and 5G | Ericsson, Nokia, Samsung, Keysight, Rohde and Schwarz | DSP, high-speed I/O, RTL design |
| Data centre and finance | Hyperscalers, trading firms, Napatech, Jane Street and peers | Low-latency networking, Vitis and RTL kernels |
| Aerospace and defence | Airbus, Thales, BAE Systems, Lockheed Martin, national agencies | Reliability, security clearance, VHDL often required |
| Industrial, automotive, medical | Siemens, Bosch, Philips, test and measurement firms | Safety standards, long product life, mixed signal |
| Research | CERN, universities, national laboratories | Trigger and DAQ systems, hls4ml, open tools |
Common mistakes
- Learning two HDLs badly instead of one well. Pick Verilog or VHDL by the employers you want, then learn the other later.
- Skipping simulation. An engineer who debugs only on hardware is slow and interviews poorly.
- Listing tools on a CV rather than designs. Employers want to know what you built and what broke.
- Ignoring the software side on SoC roles, or the hardware side on embedded roles.
- Treating certifications as a substitute for a portfolio.
- Accepting the first pay figure found online as the market. Ask people in your region and segment.
Going deeper
- ACM/SIGDA International Symposium on FPGAs, the main academic venue and a good read on where the field is going.
- FCCM, the IEEE symposium on field-programmable custom computing machines.
- US Bureau of Labor Statistics, electrical and electronics engineers, the only free, regularly updated pay and employment series that covers the profession, for one country.
- IEEE for the standards (1364, 1800, 1076) that define the HDLs you will be tested on.
- cocotb documentation, for the Python verification route that many newer teams use.