Research digest, week of 10 November 2026
Eight recent arXiv papers on LUT-based and ternary inference, zero-skipping CNN engines, anti-tamper sensor weaknesses, homomorphic encryption, an open Spartan-6 flow, SoC simulation and HLS modelling.
The papers this week cluster around three themes, two of which touch on news from the same days.
The first is inference at the small, fast end. ConvLUT pushes LUT-based neural networks from MLPs into convolutions with sub-50 ns latency, SkipLane tidies up the accumulation path in zero-skipping CNN engines on a PYNQ-Z2, and PENSA runs a two-billion-parameter ternary LLM entirely on an Alveo U50 using HBM. All three are honest about their limits: small models, low clocks or CPU-only baselines.
The second theme is security. NonSense, posted the same day AMD announced its Versal TR devices, argues that anti-tamper sensors are a fragile attack surface and lists the physical effects most threat models ignore. The NTT paper on the Alveo V80 shows the shape of practical homomorphic encryption acceleration, and how modest the end-to-end gain is once the kernel is no longer the only bottleneck.
The third is tooling. An open, browser-based flow for Spartan-3E and Spartan-6 produces bitstreams byte-identical to ISE’s, which matters for the boards still built on those parts. Naviq offers a fast open simulator for Versal-class SoCs, and the HLS paper shows that modelling architectural state explicitly in C++ gives processor-grade results from an HLS tool.
NonSense: On the (In)security of FPGA Anti-tamper Sensors #
The authors argue that the on-chip sensors FPGAs use to detect glitching and other active physical attacks are themselves a weak point rather than a trusted foundation. Drawing on their recent experimental results, they show that both the detection and the response paths of current hard-IP and soft-IP sensors can be defeated without opening the package. They identify three effects that threat models rarely include: the power delivery network can steer a fault to its target while sparing a nearby sensor, temperature shifts detection thresholds, and ageing drifts calibration. The paper is a position piece with proposed countermeasures rather than a new attack, so read it as a checklist for anyone relying on sensor-based zeroisation.
ConvLUT: Rethinking Convolutional Architectures for Ultra-Low-Latency LUT-Based Inference #
LUT-based neural networks, where each neuron becomes a lookup table that is unrolled directly into logic, have so far been limited to MLP-style models. This paper extends the idea to convolutions, with a LUT-tree that tames the receptive-field fan-in problem, a LUT-based pooling layer and a hardware-aware pruning schedule. On the MLPerf Tiny tasks (CIFAR-10, Visual Wake Words and keyword spotting) the fully unrolled designs run with latencies below about 50 ns and beat earlier LUT-based models on CIFAR-10 by at least 20 percentage points of accuracy. The models are still small and fully unrolled, so this targets trigger-style and sensor-front-end workloads rather than general vision.
PENSA: A Spatial Accelerator for BitNet b1.58 Inference on an HBM-equipped AMD Alveo FPGA #
Ternary LLMs replace multiplications in their linear layers with sign-controlled adds, which moves the bottleneck to feeding packed weights and reducing the results. PENSA runs the full BitNet b1.58 2B4T model on an Alveo U50, streaming TQ1_0-packed weights from eight HBM pseudo-channels into two matrix engines that each handle 1,280 ternary weights per cycle, while attention and vocabulary projection stay resident on the device. At 104.1 MHz it reaches 58.09 tokens per second at a context of 128 and 24.60 at 2048, which the authors put at 2.14 to 3.14 times a Xeon E-2356G baseline. The clock is low for an UltraScale+ part and the comparison is against a CPU rather than a GPU, so treat it as a feasibility result.
SkipLane: Write-Once, Conflict-Free Accumulation for Zero-Skipping CNN Engines on FPGAs #
Skipping zero activations in a CNN engine saves multiplies but makes accumulation messy, because products from a compressed window land in different output columns. The authors' earlier design merged them with read-modify-write on a row buffer, which made sparse inputs slower than dense ones. SkipLane gives each kernel row its own lane with three partial-sum registers, retires finished columns into banks that cannot conflict, and defers all cross-lane summation to readout, so nothing is ever read back. Six engines meet 140 MHz on a PYNQ-Z2 in 21.1k LUTs and run LeNet-5 bit-exactly, with conv1 needing 1.94 times fewer cycles than a dense engine. On the narrow conv2 layer it is slower than dense, a reminder that sparsity schemes depend heavily on layer shape.
An Open Implementation Flow for the Xilinx Spartan-3E and Spartan-6 that Runs in the Browser, Checked Byte for Byte Against ISE #
This single-author paper describes a complete open flow, from HDL to bitstream, for Spartan-3E (XC3S100E to XC3S1200E) and two Spartan-6 parts, families that only the discontinued ISE 14.7 can target. Yosys and nextpnr are compiled to WebAssembly, nextpnr's Himbaechel framework is fed generated Spartan architectures, and a custom bitstream writer refuses to emit any feature whose bits were not measured. The bit database was built by black-box experiments against ISE's XDL and bitgen tools, and for the same placed-and-routed design the output is byte-identical to bitgen's. Across 67 open designs on the XC3S1200E the flow used 15 per cent fewer slices with 14 per cent shorter critical paths than ISE at the Area goal, though at the Fast goal its paths were 12 per cent longer. It ships as the Apache-2.0 npm package silinx-fpga.
Naviq: An Open-Source System-on-Chip Simulator for Rapid Prototyping, Verification, and Design Space Exploration #
Modern FPGA SoCs such as Versal combine programmable logic with hard processors and a network on chip, and the interaction between them dominates performance. Vendor simulation captures this but is slow, while generic software models abstract too much. Naviq is an open-source cycle-level simulator in C++ that models the hardened infrastructure, including an AXI4-compliant NoC with packetisation, routing and backpressure, and plugs in user accelerators through Verilator. The authors report that it reproduces the bandwidth and latency of Vivado's RTL NoC model while running 81 to 182 times faster on the workloads they evaluated. It is tuned to Versal-class devices, so its accuracy on other architectures is untested.
A State Augmented Approach to Paralle Modeling in High-Level Synthesis #
HLS can only schedule the concurrency its input makes legal, and a plain sequential C++ model of a feedback-coupled design such as a processor hides the state boundaries the tool needs. The authors model the design as synchronous sequential processes that start together and synchronise on completion, keeping persistent state and feedback explicit in C++ while HLS schedules the operations inside each process. A five-stage RV32I core written this way reaches 1.221 cycles per instruction at 220 MHz on a Kintex UltraScale+, against 4.000 for a naive HLS version and 1.575 at 242 MHz for the hand-written Ibex core. An area-tuned variant cuts LUTs by 65 per cent at the cost of 9.7 per cent more cycles. The result depends on the designer taking back control of architecture, which is the opposite of what HLS marketing promises.
End-to-End NTT on FPGA for FHE Acceleration #
The number theoretic transform and its inverse take about 63 per cent of CPU time in FHE-based neural network inference, so the authors build a fully unrolled, delay-commutator streaming NTT kernel and floorplan it across the three dies of an AMD Alveo V80. At 400 MHz it transforms a 65,536-coefficient polynomial every 5.12 microseconds, which they state is the highest FPGA throughput at that size, and it is up to 22 times faster than the CPU per transform when offloaded. Integrated into the Lattigo library with 128-bit secure parameters, it speeds up key switching and bootstrapping by 1.8 to 2.2 times and end-to-end inference by 1.8 to 2.1 times. The modest end-to-end gain compared with the kernel speed-up shows how much of FHE is not the NTT.