Open-source toolchains

Overview

Until 2015 every FPGA bitstream format was secret and every FPGA design went through the vendor’s tools. That changed when Project IceStorm documented the Lattice iCE40 bitstream and Yosys gained a place-and-route partner. Today a fully open flow (synthesis, place and route, bitstream generation, programming) exists for several families, with Lattice iCE40 and ECP5 and Gowin GW1N and GW2A the ones you can rely on for real products. This hub is for engineers who want to know what the open flow can do, what it cannot, and whether it is the right choice for a given device.

The appeal is practical as much as ideological. The tools install in seconds, run from the command line, script in Python, run in CI, and build a small design in seconds rather than minutes. The cost is a smaller supported device list, no vendor support, and timing-driven routing that is good but not yet at vendor level on the larger families.

Key ideas

The three stages and who does what

Yosys is the synthesiser. It reads Verilog (and SystemVerilog and VHDL through plugins or the commercial Tabby CAD version), optimises, and maps to the target’s cells. ABC does the logic optimisation underneath. nextpnr places and routes using a database of the device’s internals and emits a text description of the configuration. A per-family packer (icepack, ecppack, gowin_pack, prjoxide) turns that into a bitstream. openFPGALoader, or the older iceprog and similar, pushes it into the device or its flash. Each stage is a separate program with a documented file in between, which is what makes the flow scriptable.

Support is per family, and uneven

At the time of writing the picture is roughly this. iCE40 (all variants including UltraPlus) is mature: the open flow is the one most users choose and Lattice has quietly accepted it. ECP5 is mature, including the SerDes, and the ULX3S and OrangeCrab boards exist because of it. Gowin GW1N and GW2A through Apicula are good for logic, block RAM and PLLs, with newer GW5A support arriving. Lattice Nexus (CrossLink-NX, Certus-NX) through Project Oxide works but has fewer users. AMD 7 Series through Project X-Ray and nextpnr-xilinx can build real designs on Artix-7 but lacks full timing data and some hard blocks, so it remains for the curious rather than for products. Altera Cyclone V has had the Mistral project, early stage. Microchip, Efinix and the big AMD and Altera families have no open bitstream support, and Efinix in particular has said it does not intend to publish its format.

What the open flow does not do

Timing analysis exists in nextpnr but relies on delay models that are only as complete as the reverse engineering. For iCE40 and ECP5 the models are good enough that a design that passes nextpnr timing runs. There is no power estimator, no formal equivalence check against the vendor tools, no encrypted bitstream generation, and limited support for partial reconfiguration or the vendor’s hard IP such as PCIe and DDR controllers (ECP5 DDR3 works through LiteDRAM, a soft controller). Synthesis quality from Yosys is close to vendor tools on LUT count for typical designs but can be worse on carry chains and DSP inference unless you write RTL the way the mapper expects. For large commercial designs on AMD or Altera parts the vendor tools remain the only practical route, and OpenFPGA sits in a different space: it generates the FPGA itself, for people designing new programmable fabrics.

Where to start

The cheapest way to learn FPGAs end to end is an iCEBreaker or Tang Nano 9K and the OSS CAD Suite nightly build, which bundles Yosys, nextpnr, the packers, openFPGALoader, Verilator and Icarus Verilog in one archive. Read /learn/beginner/05-your-first-hdl-module/ and /learn/beginner/06-simulation-and-testbenches/, both of which run on the open simulators, then /learn/beginner/10-from-rtl-to-board/ for the build step. Compare the open flow and the vendor flow on the same board, because knowing both is the useful skill. An intermediate track on scripted and CI-driven flows is coming.

Tools and vendors

F4PGA (formerly SymbiFlow, under CHIPS Alliance) packaged the X-Ray and Trellis work with VPR as an alternative router. Its development slowed after 2022 and most activity moved to the YosysHQ repositories, so treat its documentation as historical where it conflicts with the nextpnr readme.

Common mistakes

• Assuming the open flow supports whatever board you already own. Check the family first.
• Trusting a design that routes but has no timing constraints. Give nextpnr the clock frequency and read the report.
• Writing vendor-primitive-heavy RTL, then expecting Yosys to infer the same structures. Keep inference-friendly code or instantiate the open-flow primitive names.
• Using an old distribution package of Yosys. The flow moves fast, and the OSS CAD Suite nightly is the supported route.
• Confusing simulation tools with synthesis tools. Verilator and GHDL work for every vendor’s designs and are the easiest first step into open tooling.

Going deeper

• Yosys manual and the Yosys repository.
• nextpnr repository, with per-architecture documentation and status.
• Project IceStorm, Project Trellis, Apicula, Project Oxide and Project X-Ray.
• openFPGALoader, which programs nearly every board and cable in use.
• OSS CAD Suite builds, the one-archive install.
• OpenFPGA, for generating new fabrics rather than targeting existing ones.