Yosys 0.71 reimplements strings and lifts the multiplier size limit in the MCM pass
The November release of the open-source synthesis tool changes its internal string storage, which may break plugins, adds a shuffle pass and FPGA target options, and fixes out-of-memory crashes on large case statements.
YosysHQ published Yosys 0.71 on 12 November 2026, one month after 0.70. The largest internal change is a new string implementation that deduplicates common prefixes to improve performance. The release notes warn that plugins may need to be adapted and point to the idstring page in the internals documentation. Related to this, the dump and write_rtlil passes gain -readable and -small options that control how identifiers are printed.
The multiple-constant-multiplication (MCM) pass now uses the HCUB algorithm, which the notes say improves runtime on big multipliers and removes the previous 32-bit maximum size. A new shuffle pass reorders design objects deterministically, which is handy for checking that a downstream flow does not depend on object order. The verific and read_slang front ends gain experimental -target and -family options for naming an FPGA synthesis target. The write_verilog pass gains -nodec_attr and -dec_param for compatibility with other tools. Among the fixes, out-of-memory crashes on large casez and priority case statements have been resolved, and the Verific front end detects unsupported SystemVerilog assertion constructs more reliably.
At the time of writing nextpnr has had no matching release. Its latest is 0.11.1 from August 2026, so the place-and-route half of the open flow for iCE40, ECP5 and Gowin parts is unchanged.
Why it matters
If you build Yosys plugins, or depend on tools that do, test against 0.71 before moving production flows: the string change touches the identifier type used throughout the C++ API. For most users the MCM and casez fixes are the practical gains, particularly in DSP-heavy designs that synthesise constant multipliers into shift-and-add trees. The -target and -family options hint at a tighter link between the commercial Verific front end and FPGA-specific synthesis, though they are marked experimental. Monthly releases mean the version pinned in your build container is probably already behind.